EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 56

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Memory Chip Select Priority
A lower-numbered Chip Select is granted priority over a higher-numbered Chip Select.
For example, if the address space of Chip Select 0 overlaps the Chip Select 1 address
space, Chip Select 0 is active.
Reset States
On RESET, Chip Select 0 is active for all addresses, because its Lower Bound register
resets to
Lower and Upper Bound registers reset to
Memory Chip Select Example
The use of Memory Chip Selects is displayed in
values listed in
configured for memory addresses. Also, CS1 overlaps with CS0. As CS0 is prioritized
higher than CS1, CS1 is not active for much of its defined address space.
CS0_LBR = CS1_LBR = 00h
00h
CS2_UBR = CFh
CS3_UBR = FFh
CS1_UBR = 9Fh
CS0_UBR = 7Fh
CS3_LBR = D0h
CS2_LBR = A0h
and its Upper Bound register resets to
Table 13
Figure 6. Example: Memory Chip Select
on page 50. In this example, all 4 Chip Selects are enabled and
3 MB Address Space
3 MB Address Space
2 MB Address Space
8 MB Address Space
CS3 Active
CS2 Active
CS1 Active
CS0 Active
00h
.
Figure
FFh
6. The associated control register
. All of the other Chip Select
Memory
Location
FFFFFFh
D00000h
CFFFFFh
A00000h
9FFFFFh
800000h
7FFFFFh
000000h
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
49