EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 61

IC ACCLAIM MCU 128KB 100LQFP

EZ80F92AZ020EG

Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F92AZ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-3871
EZ80F92AZ020EG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F92AZ020EG
Manufacturer:
Zilog
Quantity:
10 000
Table 15. Z80 Bus Mode Write States
PS015313-0508
STATE T1
STATE T2
STATE T3
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional WAIT states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered.
Z80
The Z80 bus mode states can be configured for 1 to 15 CPU system clock cycles. In the
figures, each Z80 bus mode state is two CPU system clock cycles in duration.
Figure 10
peripheral during each Z80 bus mode cycle.
System Clock
ADDR[23:0]
®
DATA[7:0]
or IORQ
bus mode Read and Write timing is displayed in
MREQ
WAIT
CSx
WR
RD
on page 55 also display the assertion of 1 wait state (T
Figure 9.Example: Z80 Bus Mode Read Timing
T1
T2
T
CLK
Figure 9
T3
and
Chip Selects and Wait States
Product Specification
WAIT
Figure 10
eZ80F92/eZ80F93
) by the external
WAIT
) are asserted
Figure 9
on page 55.
and
54

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