EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 63

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Intel Bus Mode (Separate Address and Data Buses)
During Read operations with separate address and data buses, the Intel bus mode employs
4 states (T1, T2, T3, and T4) as listed in
Table 16. Intel Bus Mode Read States (Separate Address and Data Buses
STATE T1
STATE T2
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
The Read cycle begins in State T1. The CPU drives the address onto the
address bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
During State T2, the CPU asserts the RD signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
RD
Figure 11. Intel
TM
Multiplexed
Bus Mode
Controller
Controller
Bus Mode Signal and Pin Mapping
Bus
ADDR[7:0]
Table
16.
Intel Bus
Signal Equvalents
ALE
RD
WR
READY
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
56