EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 71

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 20. Motorola Bus Mode Read States (Continued)
Table 21. Motorola Bus Mode Write States
PS015313-0508
STATE S4
STATE S5
STATE S6
STATE S7
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
STATE S6
STATE S7
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
During state S5, no bus signals are altered.
During state S6, data from the external peripheral device is driven onto the data bus.
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each WAIT state is a full bus mode cycle.
On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at
this time.
The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/
W Low).
Entering S1, the CPU drives a valid address on the address bus.
On the rising edge of S2, the CPU asserts AS and drives R/W Low.
During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T
DTACK is asserted. Each WAIT state is a full bus mode cycle.
During S5, no bus signals are altered.
During S6, no bus signals are altered.
Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the
CPU drives R/W High. The peripheral device deasserts DTACK at this time.
The eight states for a Write operation in Motorola bus mode are listed in
WAIT
) states until DTACK is
Chip Selects and Wait States
Product Specification
WAIT
eZ80F92/eZ80F93
Table
) states until
21.
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