EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 80

IC ACCLAIM MCU 128KB 100LQFP

EZ80F92AZ020EG

Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F92AZ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-3871
EZ80F92AZ020EG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F92AZ020EG
Manufacturer:
Zilog
Quantity:
10 000
PS015313-0508
Watchdog Timer Operation
Enabling and Disabling the WDT
The Watchdog Timer is disabled upon a RESET. To enable the WDT, the application
program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the
WDT cannot be disabled without a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—2
clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the
WDT_CTL register (WDT_CTL[1:0]). The approximate time-out period for two
different WDT clock sources is listed in
Table 26. Watchdog Timer Approximate Time-Out Delays
RESET Or NMI Generation
On a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In addition,
the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the CPU.
The default operation is for the WDT to cause a RESET. It asserts/deasserts on the rising
edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the source
of the RESET event.
Clock Source
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
Note: *WDT time-out values should be sufficiently long to allow Flash
operations to complete.
Divider Value
2
2
2
2
2
2
2
2
2
2
2
2
18
22
25
27
18
22
25
27
18
22
25
27
Table
26.
Time Out Delay
209.7 ms*
13.1 ms*
83.9 ms
4096 s
5.2 ms
1024 s
1.68 s
6.71 s
0.67 s
2.68 s
8.00 s
128 s
18
, 2
22
Product Specification
, 2
25
eZ80F92/eZ80F93
, and 2
Watchdog Timer
27
system
73

Related parts for EZ80F92AZ020EG