EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 92

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Note:
Timer Reload Register—High Byte
The Timer Reload Register—High Byte, listed in
byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload
value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
Table 36. Timer Reload Register—High Byte(TMR0_RR_H = 0082h, TMR1_RR_H =
0085h, TMR2_RR_H = 0088h, TMR3_RR_H = 008Bh, TMR4_RR_H = 008Eh, or
TMR5_RR_H = 0091h)
Timer Input Source Select Register
The Timer Input Source Select register, listed in
for Programmable Reload Timer 0–3 (TMR0, TMR1, TMR2, TMR3). Event frequency
must be less than one-half of the system clock frequency. When configured for event
inputs through the port pins, the Timers decrement on the fifth system clock rising edge
following the rising edge of the port pin. The timer event input can arrive from the GPIO
port, the real-time clock, or the system clock. The value of the clock divider in the Timer
Control Register is ignored when the timer event input is either from the GPIO port pin or
the real-time clock source.
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
TMRx_RR_H
The Timer Data registers and Timer Reload registers share the same address
space.
Value
00h–FFh These bits represent the High byte of the 2-byte timer
W
7
0
Description
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.
W
6
0
W
5
0
Table 37
Table
W
4
0
36, stores the most-significant
on page 86, sets the input source
W
3
0
Programmable Reload Timers
Product Specification
W
2
0
eZ80F92/eZ80F93
W
1
0
W
0
0
85