ST10R172LT6 STMicroelectronics, ST10R172LT6 Datasheet
ST10R172LT6
Specifications of ST10R172LT6
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ST10R172LT6 Summary of contents
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High Performance 16-bit CPU CPU Frequency MHz 40ns instruction cycle time at 50-MHz CPU clock 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit manipulation facilities Additional instructions to support HLL and operating systems ...
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PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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P4.3/A19 P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD W R/W RL READY/READY ALE RPD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 ...
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P5.10 98-100 I –P5. 100 XTAL1 5 I XTAL2 6-bit input-only port with Schmitt-Trigger characteristics. Port 5 pins also serve as timer inputs: ...
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ST10R172L - PIN DESCRIPTION P3.0 – 8-21 I/O P3.13 P3. 15-bit ...
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P4.0– 23-26 I/O P4.7 29-32 ... ... I WR WRL READY READY 5T An 8-bit bidirectional I/O port. ...
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ST10R172L - PIN DESCRIPTION ALE PORT0: I/O P0L.0– P0L.7, P0H P0H.7 PORT1: I/O P1L.0– 59- 66 P1L.7, P1H.0 - 67, 68 P1H.7 71-76 8/ Address Latch ...
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RSTIN RSTOUT NMI 81 I P6.0- 82-89 I/O P6 ... ... I Reset Input with Schmitt-Trigger characteristics. Resets the device when a low level is applied ...
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ST10R172L - PIN DESCRIPTION P2.8 – I/O P2. ... ... 93 I P7.0 – I/O P7 RPD 38, 49, 69 ...
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FUNCTIONAL DESCRIPTION ST10R172L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different on- chip components and the internal bus structure. EA, ALE, RD, WR/WRL, READY, NMI, ...
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ST10R172L - MEMORY MAPPING 3 MEMORY MAPPING The ST10R172L is a ROMless device, the internal RAM space is 1 KByte. The RAM address space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h - 00’FCFFh) ...
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CENTRAL PROCESSING UNIT The main core of the CPU contains a 4-stage instruction pipeline, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one machine cycle requiring 40ns at ...
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ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10R172L supports several mechanisms for fast and flexible response to the service requests that can be generated from various sources, internal or external to the ...
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Interrupt Sources Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register ...
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ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5.2 Hardware traps Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table ...
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PARALLEL PORTS The ST10R172L provides I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. ...
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ST10R172L - PWM MODULE of external memory space, the address space can be restricted to 1 MByte, 256 KByte KByte. 8 PWM MODULE A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width ...
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GENERAL PURPOSE TIMERS The GPTs are flexible multifunctional timer/counters used for time-related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit contains five 16-bit timers, organized in ...
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ST10R172L - GENERAL PURPOSE TIMERS Timer input selection F =50MHz CPU 000b 001b Prescaler 8 16 Factor Input 6.25 MHz 3.125 Frequency MHz Resolution 160ns 320ns Period 10.49ms 20.97ms Table 5 GPT1 timer input frequencies, resolution and periods T2E UD ...
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GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable ...
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ST10R172L - SERIAL CHANNELS T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD 10 SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with ...
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S0BRS = ‘0’ 50MHz CPU Baud Rate Deviation Error (Baud) 1562500 0.0% / 0.0% 56000 +3.3% / -0.4% ...
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ST10R172L - WATCHDOG TIMER SSPCKS Value 011 SSP clock = CPU clock divided by 16 100 SSP clock = CPU clock divided by 32 101 SSP clock = CPU clock divided by 64 110 SSP clock = CPU clock divided ...
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SYSTEM RESET The following type of reset are implemented on the ST10R172L: Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock signal on XTAL1 not internally resynchronized, it resets the microcontroller into its default ...
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ST10R172L - POWER REDUCTION MODES 13 POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle ...
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Physical Name Address CC9IC b FF8Ah CC10IC b FF8Ch CC11IC b FF8Eh CP FE10h CRIC b FF6Ah CSP FE08h DP0L b F100h E DP0H b F102h E DP1L b F104h E DP1H b F106h E DP2 b FFC2h DP3 b ...
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ST10R172L - SPECIAL FUNCTION REGISTERS Physical Name Address MDH FE0Ch MDL FE0Eh ODP2 b F1C2h E ODP3 b F1C6h E ODP6 b F1CEh E ODP7 b F1D2h E ONES FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H ...
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Physical Name Address PSW b FF10h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E RP0H b F108h E S0BG FEB4h S0CON b FFB0h S0EIC b FF70h S0RBUF FEB2h S0RIC b FF6Eh S0TBIC b F19Ch E S0TBUF ...
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ST10R172L - SPECIAL FUNCTION REGISTERS Physical Name Address T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC b FF66h T6 FE48h T6CON b FF48h T6IC b FF68h ...
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ELECTRICAL CHARACTERISTICS 15.1 Absolute Maximum Ratings • Ambient temperature under bias ( T • Storage temperature ( T • Voltage on V pins with respect to ground ( V DD • Voltage on any pin with respect to ground ...
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ST10R172L - ELECTRICAL CHARACTERISTICS Remarks on 5 volt tolerant (5T) and 5 volt fail-safe (5S) pins The 5V tolerant input and output pins can sustain an absolute maximum external voltage of 5.5V. However, signals on unterminated bus lines might have ...
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DC Characteristics = 3.3V 0. Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN, RPD Input high voltage XTAL1 Output low voltage (ALE, RD, WR, BHE, CLKOUT, , ...
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ST10R172L - ELECTRICAL CHARACTERISTICS Parameter 3 PORT0 configuration current 2 RPD pulldown current XTAL1 input current 6) Pin capacitance (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current 1) This specification is not valid for outputs ...
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Figure 7 Supply/idle current vs operating frequency ST10R172L - ELECTRICAL CHARACTERISTICS CCmax I IDmax 50 f [MHz] CPU 35/68 1 ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 15.3 AC Characteristics Test conditions • Input pulse levels: ........................................................................................... 0 to +3.0 V • Input rise and fall times (10%-90%):........................................................................ 2.5 ns • Input timing reference levels: ................................................................................. +1.5 V • Output timing reference levels: ...
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From output under test +0.15 V LOAD V LOAD V - 0.15 V LOAD V OL For timing purposes a port pin is no longer floating when a 150 mV change from ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.1 Cpu Clock Generation Mechanisms ST10R172L internal operation is controlled by the CPU clock f clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external timing (AC Characteristics) specification therefore depends on ...
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P0.15-13 (P0H.7- Table 12 CPU clock generation mechanisms 1) The maximum depends on the duty cycle of the external clock signal. The maxi- mum input ...
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ST10R172L - ELECTRICAL CHARACTERISTICS Note The address float timings in Multiplexed bus mode (t TCL = 1 f max XTAL Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers ...
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N = number of consecutive TCLs and 1 and 3TCL min PLL jitter is an important factor for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For slower operations and longer periods (e.g. pulse ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.2 Memory Cycle Variables The timing tables below use three variables derived from the BUSCONx registers and represent programmed memory cycle characteristics. Table 13 describes how these variables are computed. Description ALE Extension Memory Cycle Time ...
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Multiplexed Bus 3 ALE cycle time = 6 TCL + 2 A Parameter Symbol ALE high time t 5 Address (P1, P4), BHE t 6 setup to ALE t Address ...
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ST10R172L - ELECTRICAL CHARACTERISTICS Parameter Symbol Data hold after rising edge Data float after RD rising t 19 12)) edge t Data valid Data hold after ALE rising edge after RD, ...
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Parameter Symbol RdCS to Valid Data (with RW delay) RdCS to Valid Data (no RW delay) RdCS, WrCS Low Time t 48 (with RW delay) RdCS, WrCS Low Time t 49 (no RW delay) ...
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ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT ALE CSx A23-A16 (A15-A8) BHE Read Cycle BUS P0 RD Write Cycle BUS P0 WR, WRL, WRH multiplexed bus, with/without read/write delay, normal ALE 46/ 38u ...
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CLKOUT t 5 ALE t 38u CSx t 6d/b A23-A16 (A15-A8) BHE Read Cycle t 6m BUS P0 RD Write Cycle BUS P0 WR WRL, WRH Figure 14 External memory cycle: multiplexed bus, with/without read/write delay, extended ALE ST10R172L - ...
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ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t 5 ALE t 6b/d A23-A16 (A15-A8) BHE t 6m Read Cycle BUS P0 RdCSx Write Cycle BUS P0 WrCSx multiplexed bus, with/without read/write delay, normal ALE, read/write chip select 48/ ...
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CLKOUT t 5 ALE t 6d/b A23-A16 (A15-A8) BHE Read Cycle t 6m BUS P0 RdCSx Write Cycle BUS P0 WR WRL, WRH Figure 16 External memory cycle: multiplexed bus, with/without read/write delay, extended ale, read/write chip select ST10R172L - ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.4 Demultiplexed Bus 3 ALE cycle time = 4 TCL + 2 A Parameter ALE high time Address (P1, P4), BHE setup to ALE Address setup to ...
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Parameter Symbol Data hold after WR t ALE rising edge after RD Address hold after RD Address hold after WRH t Latched CS setup to ALE t Unlatched CS setup to ALE t Latched CS low ...
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ST10R172L - ELECTRICAL CHARACTERISTICS Parameter Data hold after RdCS Data float after RdCS 1 2 (with RW-delay) Data float after RdCS 1 2 (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS 1) Output loading is specified using ...
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CLKOUT t 5 ALE t 38u CSx A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7- Write Cycle P0 BUS (D15-D8) D7- WR(L), WRH Figure 17 External memory cycle: demultiplexed bus, with/without read/write delay, normal ...
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ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT ALE t CSx A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RD Write Cycle P0 BUS (D15-D8) D7-D0 WR(L), WRH demultiplexed bus, with/without read/write delay, extended ALE 54/ 38u ...
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CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RdCsx Write Cycle P0 BUS (D15-D8) D7-D0 WrCSx demultiplexed bus, with/without read/write delay, normal ALE, read/write chip select ST10R172L - ELECTRICAL CHARACTERISTICS ...
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ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RdCSx Write Cycle P0 BUS (D15-D8) D7-D0 WrCSx demultiplexed bus, no read/write delay, extended ALE, read/write chip select 56/ ...
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CLKOUT and READY/READY 3 Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time 1) CLKOUT rise time 1 CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY ...
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ST10R172L - ELECTRICAL CHARACTERISTICS t 32 CLKOUT ALE Command RD, WR Sync READY t 58 Async 3) READY Sync READY t 58 Async 3) READY Figure 21 CLKOUT and READY/READY 1 Cycle as programmed, including MCTC waitstates (Example shows 0 ...
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Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.6 External Bus Arbitration 3 Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay ...
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CLKOUT t 61 HOLD HLDA 1) BREQ CSx (On P6.x) Other Signals Figure 22 External bus arbitration, releasing the bus 1 The ST10R172L will complete the running bus cycle before granting bus access. 2 This is the first opportunity for ...
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ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 23 External bus arbitration, (regaining the bus) 1 This is the last chance for BREQ to trigger the regain-sequence indicated. Even if BREQ is ...
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External Hardware Reset = 3 Parameter Symbol 1) t Sync. RSTIN low time 70 RSTIN low to internal t 71 reset sequence start internal reset sequence (RSTIN internally pulled low) RSTIN rising ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 1) RSTIN Internal Reset Signal ALE RD PORT0 PORT1 (Demux Bus) 5) RSTOUT 6) Other IOs t 77 Figure 24 External asynchronous hardware reset (power-up reset): Vpp low 1 The ST10R172L is reset in ...
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RSTIN t 711) Internal Reset Signal ALE RD PORT0 PORT1 (Demux Bus) 6) RSTOUT 7) Other IOs t 77 Figure 25 External synchronous hardware reset (warm reset): Vpp high 1 The pending internal hold states ...
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ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.8 Synchronous Serial Port Timing = 3 Parameter SSP clock cycle time SSP clock high time SSP clock low time SSP clock rise time SSP clock fall time CE ...
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SSPCLK t 205 SSPCEx t 207 SSPDAT 1) SSPCLK SSPCEx SSPDAT last Wr. Bit 1 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold). 2 The ...
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... ORDERING INFORMATION Sales type ST10R172LT1 ST10R172LT6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...