EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

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Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
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eZ80AcclaimPlus!™ Connectivity ASSP
eZ80F91 ASSP
Product Specification
PS027001-0707
Copyright ©2007 by Zilog, Inc. All rights reserved.
www.zilog.com

Related parts for EZ80F91AZA50EG

EZ80F91AZA50EG Summary of contents

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... Connectivity ASSP eZ80F91 ASSP Product Specification PS027001-0707 Copyright ©2007 by Zilog, Inc. All rights reserved. www.zilog.com ...

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... No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. Zilog is a registered trademark of Zilog Inc. in the United States and in other countries. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners ...

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Revision History Each instance in the Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Revision Date Level Section July 2007 ...

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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Zilog Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Operation of the eZ80F91 Device during ZDI Break Points . . . . . . . . . . . . . . . 242 Bus Requests During ZDI Debug Mode ...

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EMAC Operation in HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Architectural Overview Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80AcclaimPlus!™ Flash ASSPs. The eZ80F91 is an high-speed ASSP with a maximum clock speed of 50 MHz and single-cycle instruction fetch. It operates in Z80 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80F91 makes it suitable for a variety of applications, including industrial control, embedded communication, and point-of-sale terminals ...

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IEEE 1149.1-compatible JTAG • 144-pin LQFP and BGA packages • 3.0–3.6 V supply voltage with 5 V tolerant inputs • Operating Temperature Range: Standard: 0 ºC to +70 ºC – Extended: –40 ºC to +105 ºC – Note: All ...

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RTC_V Real-Time DD Clock and RTC_X IN 32 KHz Oscillator RTC_X OUT SCL Serial Interface SDA SCK SPI SS Serial Parallel MISO Interface MOSI WP CTS0/1 DSR0/1 UART DCD0/1 Universal DTR0/1 Asynchronous Receiver/ RI0/1 Transmitter RTS0/1 (2) ...

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Pin Description Table 1 lists the pin configuration of the eZ80F91 device in the 144-ball BGA package. Table 1. eZ80F91 144-Ball BGA Pin Configuration SDA SCL PA0 PA4 B V PHI PA1 PA3 SS C ...

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Figure 2 illustrates the pin layout of the eZ80F91 device in the 144-pin LQFP package A10 A11 A12 A13 A14 ...

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Pin Characteristics Table 2 describes the pins and functions of the eZ80F91 144-pin LQFP package and 144- ball BGA package. Table 2. Pin Identification on the eZ80F91 Device LQFP BGA Pin No Pin No Symbol Function 1 A1 ADDR0 2 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 17 F1 ADDR12 Address Bus 18 F2 ADDR13 Address Bus 19 F3 ADDR14 Address Bus 20 F4 ADDR15 Address Bus 21 G1 ADDR16 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 39 L2 DATA0 40 K3 DATA1 41 J4 DATA2 42 M3 DATA3 43 L3 DATA4 44 H5 DATA5 45 L4 DATA6 46 M4 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 53 M6 INSTRD 54 L6 WAIT 55 K6 RESET Reset 56 J6 NMI 57 M7 BUSREQ 58 L7 BUSACK ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 61 M8 RTC_X RTC_X OUT 63 J7 RTC_V HALT_SLP HALT and 66 H7 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 70 M10 TDO JTAG Test 71 L10 TRST 72 M11 M12 PD0 GPIO Port D TxD0 IR_TxD 74 L12 PD1 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 75 L11 PD2 GPIO Port D RTS0 76 K10 PD3 CTS0 77 J9 PD4 DTR0 PS027001-0707 Signal Direction Description Bidirectional Request to Output, ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 78 K12 PD5 DSR0 79 K11 PD6 DCD0 80 H8 PD7 RI0 81 J11 J12 J10 LOOP_FILT ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 86 H11 H10 PLL_V G12 G11 PC0 GPIO Port C TxD1 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 92 G9 PC2 GPIO Port C RTS1 93 F12 PC3 GPIO Port C CTS1 94 F11 PC4 GPIO Port C DTR1 PS027001-0707 Signal ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 95 F10 PC5 GPIO Port C DSR1 96 G8 PC6 GPIO Port C DCD1 97 E12 PC7 RI1 98 E11 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 100 E10 PB0 GPIO Port B IC0 EC0 101 D12 PB1 GPIO Port B IC1 102 F8 PB2 GPIO Port B SS PS027001-0707 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 103 D11 PB3 GPIO Port B SCK 104 E9 PB4 GPIO Port B IC2 105 D10 PB5 GPIO Port B IC3 PS027001-0707 Signal ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 106 C12 PB6 GPIO Port B MISO 107 C11 PB7 GPIO Port B MOSI 108 B12 V SS 109 A12 SDA 110 A11 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 114 A10 PA0 GPIO Port A PWM0 OC0 115 B10 PA1 GPIO Port A PWM1 OC1 116 E8 PA2 GPIO Port A PWM2 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 117 B9 PA3 GPIO Port A PWM3 OC3 118 A9 PA4 GPIO Port A PWM0 TOUT0 119 C9 PA5 GPIO Port A PWM1 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 120 F7 PA6 GPIO Port A PWM2 EC1 121 A8 PA7 GPIO Port A PWM3 122 123 ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 127 C7 TxD2 MII Transmit 128 D7 TxD1 MII Transmit 129 A6 TxD0 MII Transmit 130 B6 Tx_EN MII Transmit 131 C6 Tx_CLK ...

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Table 2. Pin Identification on the eZ80F91 Device (Continued) LQFP BGA Pin No Pin No Symbol Function 137 A4 Rx_DV MII Receive 138 E6 RxD0 139 B4 RxD1 140 D5 RxD2 141 C4 RxD3 142 A3 MDC PS027001-0707 Signal Direction ...

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... External Crystal Oscillator— one mode, the not connected. In the other mode, the X Crystals recommended by Zilog are defined MHz–3 overtone circuit or 1–10 MHz range fundamental for PLL operation. For details, see 339. Real Time Clock— the on-chip 32768 Hz crystal oscillator or a 50/60 Hz power-line frequency input. While intended for timekeeping, the RTC 32 kHz oscillator is selected as an SCLK ...

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... MHz to 10 MHz generates an SCLK MHz. For more- details, see Phase-Locked Loop SCLK Source Selection Example For additional SCLK source selection examples, refer to Crystal Oscillator Guidelines for eZ80 and eZ80Acclaim! Devices Technical Note (TN0013) available on www.zilog.com. PS027001-0707 Product Specification on page 269. eZ80F91 ASSP ...

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Register Map All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all I/O operations (ADDR[23:16] = XX). All I/O operations using ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 0025 EMAC_STAD_0 0026 EMAC_STAD_1 0027 EMAC_STAD_2 0028 EMAC_STAD_3 0029 EMAC_STAD_4 002A EMAC_STAD_5 002B EMAC_TPTV_L 002C EMAC_TPTV_H 002D EMAC_IPGT 002E EMAC_IPGR1 002F EMAC_IPGR2 0030 EMAC_MAXF_L 0031 EMAC_MAXF_H 0032 EMAC_AFR 0033 EMAC_HTBL_0 0034 EMAC_HTBL_1 ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 003E EMAC_RGAD 003F EMAC_FIAD 0040 EMAC_PTMR 0041 EMAC_RST 0042 EMAC_TLBP_L 0043 EMAC_TLBP_H 0044 EMAC_BP_L 0045 EMAC_BP_H 0046 EMAC_BP_U 0047 EMAC_RHBP_L 0048 EMAC_RHBP_H 0049 EMAC_RRP_L 004A EMAC_RRP_H 004B EMAC_BUFSZ 004C EMAC_IEN 004D EMAC_ISTAT ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic Ethernet Media Access Controller, continued 0053 EMAC_TRP_L 0054 EMAC_TRP_H 0055 EMAC_BLKSLFT_L 0056 EMAC_BLKSLFT_H 0057 EMAC_FDATA_L 0058 EMAC_FDATA_H 0059 EMAC_FFLAGS PLL 005C PLL_DIV_L 005D PLL_DIV_H 005E PLL_CTL0 005F PLL_CTL1 Timers and PWM 0060 ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 0069 TMR1_DR_H TMR1_RR_H 006A TMR1_CAP_CTL 006B TMR1_CAPA_L 006C TMR1_CAPA_H 006D TMR1_CAPB_L 006E TMR1_CAPB_H 006F TMR2_CTL 0070 TMR2_IER 0071 TMR2_IIR 0072 TMR2_DR_L TMR2_RR_L 0073 TMR2_DR_H TMR2_RR_H 0074 TMR3_CTL 0075 TMR3_IER 0076 TMR3_IIR 0077 ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 007C PWM0R_L TMR3_CAPA_L 007D PWM0R_H TMR3_CAPA_H 007E PWM1R_L TMR3_CAPB_L 007F PWM1R_H TMR3_CAPB_H 0080 PWM2R_L TMR3_OC_CTL1 0081 PWM2R_H TMR3_OC_CTL2 0082 PWM3R_L TMR3_OC0_L 0083 PWM3R_H TMR3_OC0_H PS027001-0707 Name PWM 0 Rising-Edge Register—Low Byte Timer ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 0084 PWM0F_L TMR3_OC1_L 0085 PWM0F_H TMR3_OC1_H 0086 PWM1F_L TMR3_OC2_L 0087 PWM1F_H TMR3_OC2_H 0088 PWM2F_L TMR3_OC3_L 0089 PWM2F_H TMR3_OC3_H 008A PWM3F_L 008B PWM3F_H Watchdog Timer 0093 WDT_CTL 0094 WDT_RR General-Purpose Input/Output Ports 0096 ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 0097 PA_DDR 0098 PA_ALT1 0099 PA_ALT2 009A PB_DR 009B PB_DDR 009C PB_ALT1 009D PB_ALT2 009E PC_DR 009F PC_DDR 00A0 PC_ALT1 00A1 PC_ALT2 00A2 PD_DR 00A3 PD_DDR 00A4 PD_ALT1 00A5 PD_ALT2 00A6 PA_ALT0 ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 00B3 CS3_CTL Random Access Memory Control 00B4 RAM_CTL 00B5 RAM_ADDR_U 00B6 MBIST_GPR 00B7 MBIST_EMR Serial Peripheral Interface 00B8 SPI_BRG_L 00B9 SPI_BRG_H 00BA SPI_CTL 00BB SPI_SR 00BC SPI_TSR SPI_RBR Infrared Encoder/Decoder 00BF IR_CTL ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 00C4 UART0_MCTL 00C5 UART0_LSR 00C6 UART0_MSR 00C7 UART0_SPR I<SuperscriptBold>2C 00C8 I2C_SAR 00C9 I2C_XSAR 00CA I2C_DR 00CB I2C_CTL General-Purpose Input/Output Ports 00CE PC_ALT0 00CF PD_ALT0 00CC I2C_SR I2C_CCR 00CD I2C_SRR Universal Asynchronous Receiver/Transmitter ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 00D6 UART1_MSR 00D7 UART1_SPR Low-Power Control 00DB CLK_PPD1 00DC CLK_PPD2 Real-Time Clock 00E0 RTC_SEC 00E1 RTC_MIN 00E2 RTC_HRS 00E3 RTC_DOW 00E4 RTC_DOM 00E5 RTC_MON 00E6 RTC_YR 00E7 RTC_CEN 00E8 RTC_ASEC 00E9 RTC_AMIN ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 00F2 CS2_BMC 00F3 CS3_BMC Flash Memory Control 00F5 FLASH_KEY 00F6 FLASH_DATA 00F7 FLASH_ADDR_U 00F8 FLASH_CTL 00F9 FLASH_FDIV 00FA FLASH_PROT 00FB FLASH_IRQ 00FC FLASH_PAGE 00FD FLASH_ROW 00FE FLASH_COL 00FF FLASH_PGCTL PS027001-0707 Name Chip ...

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... Loads/unloads the I register with a 16-bit value. These new instructions are: – LD I,HL (ED C7) LD HL,I (ED D7) – For more information on the CPU, its instruction set, and eZ80 programming, refer to eZ80 CPU User Manual (UM0077), available on www.zilog.com. PS027001-0707 eZ80F91 ASSP Product Specification 39 ® ...

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PS027001-0707 eZ80F91 ASSP Product Specification 40 ® eZ80 CPU Core ...

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Reset The Reset controller within the eZ80F91 device features a consistent reset function for all types of resets that affects the system. A system reset, referred in this document as RESET, returns the eZ80F91 to a defined state. All internal ...

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Power-On Reset A POR occurs every time the supply voltage to the part rises from below the Voltage Brownout threshold (V bandgap-referenced voltage detector sends a continuous RESET signal to the Reset con- troller until the supply voltage (V above ...

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POR V VBO Program Execution System Clock Internal RESET Signal Figure 4. Voltage Brownout Reset Operation PS027001-0707 Voltage Brown-out RESET mode T timer delay ANA eZ80F91 ASSP Product Specification 3.3V CC Program ...

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PS027001-0707 eZ80F91 ASSP Product Specification 44 Reset ...

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Low-Power Modes The eZ80F91 device provides a range of power-saving features. The highest level of power reduction is provided by SLEEP mode with all peripherals disabled, including VBO. The next level of power reduction is provided by the HALT instruction. ...

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The PC stops incrementing. The CPU is brought out of HALT mode by any of the following operations: • A nonmaskable interrupt (NMI). • A maskable interrupt. • A RESET via the external RESET pin driven Low. • A ...

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Table 4. Clock Peripheral Power-Down Register 1 Bit 7 Reset 0 CPU Access R/W Note: R/W = Read/Write. Bit Position Value Description 7 1 System clock to GPIO Port D is powered down. GPIO_D_OFF Port D alternate functions do not ...

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Table 5. Clock Peripheral Power-Down Register 2 Bit 7 Reset 0 CPU Access R/W Note Read Only; R/W = Read/Write. Bit Position Value Description 7 1 PHI Clock output is disabled (output is high-impedance). PHI_OFF 0 PHI Clock ...

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General Purpose Input/Output The eZ80F91 device features 32 General Purpose Input/Output (GPIO) pins. The GPIO pins are assembled as four 8-bit ports—Port A, Port B, Port C, and Port D. All port signals are configured as either inputs or outputs. ...

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Table 6. GPIO Mode Selection GPIO Px_ALT2 Px_ALT1 Px_DDR Mode Bits7:0 Bits7:0 Bits7 ...

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GPIO Mode 3—Open Drain The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode, an external pull-up resistor must connect the ...

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PC5 drives the DSR1 signal to UART1. As this signal is Low level true, the DSR1 signal to UART1 is driven to 1 when PC5 is not in alternate mode function. GPIO Mode 8—Level Sensitive Interrupt The port pin ...

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Mode 2 Mode 6 Mode 8 Mode 9 Mode 7(Input) * Reading from the Px_DR returns the value stored in this register . Figure 5. GPIO Port Pin Block Diagram for Input and Interrupt Modes Simplified GPIO Port Block Diagram ...

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GPIO Interrupts Each port pin is used as an interrupt source. Interrupts are either level- or edge-triggered. Level-Triggered Interrupts When the port is configured for level-triggered interrupts (mode 8), the corresponding port pin is open-drain. An interrupt request is generated ...

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Edge triggered interrupts are cleared by writing 1 to the corresponding bit of the Px_ALT0 register. For example, if PD4 has been set up to generate an edge triggered interrupt, the interrupt is cleared by writing Px_ALT0[4]. ...

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Port x Alternate Register 0 The Port x Alternate register 0 is used to clear edge triggered interrupts edge triggered interrupt occurs, writing 1 to the corresponding bit of this register will clear it. Table 9. Port x ...

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Interrupt Controller The interrupt controller on the eZ80F91 device routes the interrupt request signals from the internal peripherals, external devices (via the internal port I/O), and the nonmaskable interrupt (NMI) pin to the CPU. Maskable Interrupts On the eZ80F91 device, ...

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Table 12. Interrupt Vector Sources by Priority (Continued) Priority Vector Source 11 06Ch RTC 12 070h UART 0 13 074h UART 078h I 15 07Ch SPI 16 080h Port 084h Port ...

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Setting the LSB of the I register produces no effect on the interrupt vector address. Table 13. Vectored Interrupt Operation Memory ADL MADL Mode Bit Bit Operation Z80 Mode 0 0 Read the LSB of the interrupt vector placed ...

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Table 13. Vectored Interrupt Operation (Continued) Memory ADL MADL Mode Bit Bit Operation ADL Mode 1 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [8:0], by the interrupting peripheral. • IEF1 • ...

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Table 14. Interrupt Priority Registers = 0013h, INT_P4 = 0014h, INT_P5 = 0015h) Bit 7 INT_P0 Reset 0 INT_P1 Reset 0 INT_P2 Reset 0 INT_P3 Reset 0 INT_P4 Reset 0 INT_P5 Reset 0 CPU Access R/W Note Undefined; ...

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The Interrupt Vector Priority Control bits are listed in Table 15. Interrupt Vector Priority Control Bits Priority Control Bit Vector INT_P0[0] 040h INT_P0[1] 044h INT_P0[2] 048h INT_P0[3] 04Ch INT_P0[4] 050h INT_P0[5] 054h INT_P0[6] 058h INT_P0[7] 05Ch INT_P1[0] 060h INT_P1[1] 064h ...

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Table 16 (RTC) as elevated to priority Level 1. 06Ch the top ten maskable interrupts. Table 16. Example: Maskable Interrupt Priority Priority Register Setting INT_P0 02h INT_P1 08h INT_P2 02h INT_P3 00h INT_P4 00h INT_P5 00h Table 17. Example: ...

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GPIO Port Interrupts All interrupts are latched. In effect, an interrupt is held even if the interrupt occurs while another interrupt is being serviced and interrupts are disabled the interrupt lower priority. However, before the ...

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Chip Selects and Wait States The eZ80F91 generates four chip selects for external devices. Each chip select is pro- grammed to access either the memory space or the I/O space. The memory chip selects are individually programmed ...

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If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a particular chip select is valid for a single 64 KB page. Memory Chip Select Priority A lower-numbered chip select is granted priority over ...

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CS3_UBR = FFh CS3_LBR = D0h CS2_UBR = CFh CS2_LBR = A0h CS1_UBR = 9Fh CS0_UBR = 7Fh CS0_LBR = CS1_LBR = 00h Table 18. Example: Register Values for Figure 7 Memory Chip Select Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO ...

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Input/Output Chip Select Operation I/O chip selects will be active only when the CPU is performing I/O instructions. Because the I/O space is separate from the memory space in the eZ80F91 device, a conflict between I/O and memory addresses never ...

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WAIT Input Signal Similar to the programmable wait states, an external peripheral drives the WAIT input pin to force the CPU to provide additional clock cycles to complete its Read or Write opera- tion. Driving the WAIT pin Low stalls ...

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SCLK ADDR[23:0] DATA[7:0] (output) CSx MREQ RD INSTRD Figure 9. Example: Wait State Read Operation Chip Selects During Bus Request/Bus Acknowledge Cycles When the CPU relinquishes the address bus to an external peripheral in response to an external bus request ...

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CPU system clock cycles per bus mode state is also independently programmable. For Intel bus mode, multiplexed address and data are selected in which both the lower byte of the address and the data byte use the data bus, ...

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Z80 bus mode Read and Write timing is illustrated in The Z80 bus mode states are configured for CPU system clock cycles. In the fig- ures, each Z80 bus mode state is two CPU system clock cycles ...

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System Clock ADDR[23:0] DATA[7:0] CSx RD WAIT WR MREQ or IORQ Intel Bus Mode Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four-state memory transfer similar to that found on Intel-style microcontrollers. The ...

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Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Figure 12. Intel Bus Mode Signal and Pin Mapping Intel Bus Mode—Separate Address and Data Buses During Read operations with separate address and data buses, the Intel ...

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Table 21. Intel Bus Mode Read States—Separate Address and Data Buses (Continued) STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior to ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or IORQ Figure 13. Example: Intel Bus Mode Read Timing—Separate Address and Data Buses PS027001-0707 WAIT eZ80F91 ASSP Product Specification 76 T4 Chip Selects and Wait ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ Figure 14. Example: Intel Bus Mode Write Timing—Separate Address and Data Buses PS027001-0707 WAIT eZ80F91 ASSP Product Specification 77 T4 Chip Selects and Wait ...

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Intel™ Bus Mode—Multiplexed Address and Data Bus During Read operations with multiplexed address and data, the Intel™ bus mode employs 4 states—T1, T2, T3, and T4 as described in Table 23. Intel Bus Mode Read States—Multiplexed Address and Data Bus ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or IORQ Figure 15. Example: Intel Bus Mode Read Timing—Multiplexed Address and Data Bus PS027001-0707 WAIT eZ80F91 ASSP Product Specification 79 T4 Chip Selects and Wait ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ Figure 16. Example: Intel Bus Mode Write Timing—Multiplexed Address and Data Bus Motorola Bus Mode Chip selects configured for Motorola bus mode modify the CPU bus signals to ...

Page 89

Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Figure 17. Motorola Bus Mode Signal and Pin Mapping During Write operations, the Motorola bus mode employs 8 states—S0, S1, S2, S3, S4, S5, S6, and S7 ...

Page 90

Table 25. Motorola Bus Mode Read States (Continued) STATE S6 During state S6, data from the external peripheral device is driven onto the data bus. STATE S7 On the rising edge of the clock entering state S7, the CPU latches ...

Page 91

S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 18. Example: Motorola Bus Mode Read Timing PS027001-0707 eZ80F91 ASSP Product Specification Chip Selects and Wait States 83 ...

Page 92

S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 19. Example: Motorola Bus Mode Write Timing Switching Between Bus Modes When switching bus modes between Intel™ to Motorola, Motorola to Intel™, eZ80 to Motorola, or ...

Page 93

Chip Select Registers Chip Select x Lower Bound Register For Memory chip selects, the chip select x Lower Bound register (see the lower bound of the address range for which the corresponding Memory chip select (if enabled) is active. For ...

Page 94

Chip Select x Upper Bound Register For Memory chip selects, the Chip Select x Upper Bound registers, detailed in defines the upper bound of the address range for which the corresponding Chip Select (if enabled) are active. For I/O chip ...

Page 95

Chip Select x Control Register The Chip Select x Control register (see type of chip select, and sets the number of wait states. The reset state for the Chip Select 0 Control register is . 00h Table 29. Chip Select ...

Page 96

Chip Select x Bus Mode Control Register The Chip Select Bus Mode register (see Z80, Intel™, or Motorola bus modes. Changing the bus mode allows the eZ80F91 device to interface to peripherals based on the Z80, Intel™, or Motorola style ...

Page 97

Bit Position Value Description [3:0] 0000 Not valid. BUS_CYCLE 0001 Each bus mode state is 1 eZ80 clock cycle in duration. 0010 Each bus mode state is 2 eZ80 clock cycles in duration. 0011 Each bus mode state is 3 ...

Page 98

Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles Pin Symbol ADDR23..ADDR0 CS0 CS1 CS2 CS3 DATA7..0 IORQ MREQ RD WR INSTRD Normal bus operation of the eZ80F91 device using CS0 to communicate to an external peripheral is illustrated in ...

Page 99

External Master MREQ Figure 20. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation External Master MREQ Figure 21. Memory Interface Bus Operation During Bus Acknowledge Cycles During bus acknowledge cycles, the Memory and I/O chip select logic is ...

Page 100

The following chip select features are not available during bus acknowledge cycles: • The chip select logic does not insert wait states during bus acknowledge cycles regard- less of the WAIT configuration for the decoded chip select. • The bus ...

Page 101

Random Access Memory The eZ80F91 device features 8 KB (8192 bytes) of single-port data Random Access Memory (RAM) for general-purpose use and RAM for the EMAC. RAM is enabled or disabled, and it is relocated to the ...

Page 102

On-chip RAM is not accessi- ble to external devices during bus acknowledge cycles. RAM Control Registers RAM Control Register Internal general purpose RAM is disabled by clearing the GPRAM_EN bit. ...

Page 103

RAM Address Upper Byte Register The RAM_ADDR_U register defines the upper byte of the address for on-chip RAM. If enabled, RAM addresses assume priority over all Chip Selects. The external Chip Select signals are not asserted if the corresponding RAM ...

Page 104

MBIST Control There are two Memory Built-In Self-Test (MBIST) controllers for the RAM blocks on the eZ80F91. MBIST_GPR is for General Purpose RAM and MBIST_EMR is for EMAC RAM. Writing MBIST_ON starts the MBIST testing. Writing a ...

Page 105

Flash Memory The eZ80F91 device features 256 KB (262,144 bytes) of non-volatile Flash memory with Read/Write/Erase capability. The main Flash memory array is arranged in 128 pages with 8 rows per page and 256 bytes per row. In addition to ...

Page 106

Flash Memory Overview The eZ80F91 device includes a Flash memory controller that automatically converts standard CPU Read and Write cycles to the specific protocol required for the Flash memory array. As such, standard memory Read and Write instructions access the ...

Page 107

Memory Read A memory Read operation uses the address bus and data bus of the eZ80F91 device to read a single data byte from Flash memory. This Read operation is similar to reads from RAM. To perform Flash memory reads, ...

Page 108

Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). A typical sequence that performs a single-byte I/O Write is shown below. Because the Write is self-timed, ing or interrupts. 1. Write the FLASH_PAGE, FLASH_ROW, and ...

Page 109

Otherwise, the burden is on software to ensure that the 31 ms maximum cumulative programming time between erases is not exceeded for a row. Memory Write A single-byte memory Write operation uses the address bus and ...

Page 110

Information Page Characteristics As noted earlier, the information page is not accessible using memory access instructions and must be accessed via the FLASH_DATA I/O register. The Flash Page Select Register contains a bit which selects the information page for I/O ...

Page 111

Flash Data Register The Flash Data register stores the data values to be programmed into Flash memory via I/O Write operations. An I/O read of the Flash Data register returns data from Flash memory. The Flash memory address used for ...

Page 112

Flash Address Upper Byte Register The FLASH_ADDR_U register defines the upper 6 bits of the Flash memory address space. Changing the value of FLASH_ADDR_U allows on-chip 256 KB Flash memory to be mapped to any location within the 16 MB ...

Page 113

Flash Control Register The Flash Control register enables or disables memory access to Flash memory. I/O access to the Flash control registers and to Flash memory is still possible while Flash memory space access is disabled. The minimum access time ...

Page 114

Flash Frequency Divider Register The 8-bit frequency divider allows the programming of Flash memory over a range of system clock frequencies. Flash is programmed with system clock frequencies ranging from 154 kHz to 50 MHz. The Flash controller requires an ...

Page 115

Flash Write/Erase Protection Register The Flash Write/Erase Protection register prevents accidental Write or Erase operations. The protection is limited to a resolution of eight 32 KB blocks. Setting a bit to 1 protects that 32 KB block of Flash memory ...

Page 116

Bit Position [1] BLK1_PROT [0] BLK0_PROT Note: The lower 32 KB block (00000h to 07FFFh—BLK0) is called the Boot block and is protected using the external WP pin. Flash Interrupt Control Register There are two sources of interrupts from the ...

Page 117

Table 42. Flash Interrupt Control Register Bit Reset CPU Access Note: R/W = Read/Write Read Only. Read resets bits [5] and [3:0]. Bit Position [7] DONE_IEN [6] ERR_IEN [5] DONE [4] [3] WR_VIO [2] RP_TMO [1] PG_VIO [0] ...

Page 118

FLASH_DATA register causes an autoincrement of the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). See Table 43. Flash Page Select Register Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position [7] ...

Page 119

Flash Row Select Register The Flash Row Select Register is a 3-bit value used to define one of the 8 rows of Flash on a single page. This register is used for all I/O access to Flash memory. In addition, ...

Page 120

Flash Column Select Register The Flash Column Select Register is an 8-bit value used to define one of the 256 bytes of Flash memory contained in a single row. This register is used for all I/O access to Flash memory. ...

Page 121

Table 46. Flash Program Control Register Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position [7:3] [2] ROW_PGM [1] PG_ERASE [0] MASS_ERASE PS027001-0707 (FLASH_PGCTL = 00FFh ...

Page 122

PS027001-0707 eZ80F91 ASSP Product Specification 114 Flash Memory ...

Page 123

Watchdog Timer The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which places the CPU into unsuitable operating states. The eZ80F91 WDT features: • Four programmable time-out ranges (depending on the WDT ...

Page 124

WDT_CLK RTC Clock System Clock WDT Oscillator Figure 25. Watchdog Timer Block Diagram Watchdog Timer Operation Enabling and Disabling the Watchdog Timer The WDT is disabled on a RESET. To enable the WDT, the application program must set WDT_EN, which ...

Page 125

Table 47. WDT Approximate Time-Out Delays for Possible Clock Sources WDT_CLK[ 3:2] 50 MHz system Divider Timeout WDT_PERI OD[1: RESET or NMI Generation A WDT time-out causes a RESET or sends a ...

Page 126

Table 48. Watchdog Timer Control Register Bit Reset CPU Access Note Read only; R/W = Read/Write. Bit Position 7 WDT_EN 6 NMI_OUT 5 RST_FLAG 4 NMI_FLAG [3:2] WDT_CLK PS027001-0707 0/1 R/W R/W R ...

Page 127

Bit Position [1:0] WDT_PERIOD Note: When the WDT is enabled, no Writes are allowed to the WDT_CTL register. PS027001-0707 Value Description 00 WDT_CLK = 00 WDT time-out period is 2 WDT_CLK = 01 WDT time-out period is 2 WDT_CLK = ...

Page 128

Watchdog Timer Reset Register The WDT Reset register (see when an value followed by a A5h occurs between the writing of does not occur prior to completion. Any value other than register after the the timer to be reset. Table ...

Page 129

Programmable Reload Timers The eZ80F91 device features four programmable reload timers. The core of each timer is a 16-bit downcounter. In addition, each timer features a selectable clock source, adjustable prescaling and operates in either SINGLE PASS or CONTINUOUS mode. ...

Page 130

Basic Timer Operation Basic timer operation is controlled by a timer control register and a programmable reload value. The CPU uses the control register to setup the prescaling, the input clock source, the end-of-count behavior, and to start the timer. ...

Page 131

Minimum time-out duration is four times longer than the input clock period and is gener- ated by setting the clock divider ratio to 1:4 and the reload value to time-out duration is 2 erated by setting the clock divider ratio ...

Page 132

TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge and the timer continues to count until disabled. An example of the timer operating in CONTINUOUS mode is illustrated in tion is indicated in System Clock Clock Enable TMR3_CTL Write ...

Page 133

... The response of the CPU to this interrupt service request is a function of the CPU’s inter- rupt enable flag, IEF1. For more information about this flag, refer to the eZ80 Manual (UM0077) available on www.zilog.com. Timer Input Source Selection Timers 0–3 features programmable input source selection. By default, the input is taken from the eZ80F91’ ...

Page 134

System Clock Clock Enable TMR3_CTL Write (Timer Enable) T3 Count 0 Timer Out (internal) Timer Out (at pad) Figure 29. Example: PRT Timer Output Operation Table 52. Example: PRT Timer Out Parameters Parameter Timer Enable Reload Prescaler Divider = 4 ...

Page 135

The following is a list of the special features for each timer: • Timer 0 No special functions – • Timer 1 One event counter (EC0) – Two input captures (IC0 and IC1) – • Timer 2 One event counter ...

Page 136

RTC Oscillator Input When the timer clock source is the Real-Time Clock signal, the timer functions just as it does in EVENT COUNT mode, except that it samples the internal RTC clock rather than the ECx pin. Input Capture INPUT ...

Page 137

Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUTPUT COMPARE events and sets output 0 as the master result, outputs 1, 2, and 3 are caused to disregard output-specific configuration and comparison values and instead mimic the current settings ...

Page 138

Timer Registers The CPU monitors and controls the timer using seven 8-bit registers. These registers are the control register, the interrupt identification register, the interrupt enable register and the reload register pair (High and Low byte). There are also a ...

Page 139

TMR3_OC_CTL2 – • Compare Value Registers TMR3_OC3_H – TMR3_OC3_L – TMR3_OC2_H – TMR3_OC2_L – TMR3_OC1_H – TMR3_OC1_L – TMR3_OC0_H – TMR3_OC0_L – Multiple PWM mode uses the following 19 registers: • PWM Control Registers TMR3_PWM_CTL1 – TMR3_PWM_CTL2 – TMR3_PWM_CTL3 – ...

Page 140

Timer Control Register The Timer x Control Register (see enabling the timer, selecting the clock source, selecting the clock divider, selecting between CONTINUOUS and SINGLEPASS modes, and enabling the auto-reload feature. Table 54. Timer Control Register TMR2_CTL = 006Fh, TMR3_CTL ...

Page 141

RLD TIM_EN 1 Timer Interrupt Enable Register The Timer x Interrupt Enable Register (see operations. Only bits related to functions present in a given timer are active. Table 55. Timer Interrupt Enable TMR2_IER = 0070h, ...

Page 142

IRQ_ICB_EN 1 IRQ_ICA_EN 0 IRQ_EOC_EN PS027001-0707 Interrupt requests for ICx are disabled (valid only in INPUT CAPTURE mode). 0 Timer 1: the capture pin is IC1. Timer 3: the capture pin is IC3. Interrupt requests for ICx are enabled ...

Page 143

Timer Interrupt Identification Register The TImer x Interrupt Identification Register (see that the CPU determines the cause of a timer interrupt. This register is cleared by a CPU Read. Table 56. Timer Interrupt Identification Register 0067h, TMR2_IIR = 0071h, TMR3_IIR ...

Page 144

Timer Data Register—Low Byte The Timer x Data Register—Low Byte returns the Low byte of the current count value of the selected timer. The Timer Data Register—Low Byte (see timer is in operation. Reading the current count value does not ...

Page 145

Timer Data Register—High Byte The Timer x Data Register—High Byte returns the High byte of the count value of the selected timer as it existed at the time that the Low byte was read. The Timer Data Register—High Byte (see ...

Page 146

Timer Reload Register—Low Byte The Timer x Reload Register—Low Byte (see (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer on end-of-count. When the reload bit (TMRx_CTL[RLD]) is set to ...

Page 147

Timer Reload Register—High Byte The Timer x Reload Register—High Byte (see (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer upon end-of-count. When the reload bit (TMRx_CTL[RLD]) is set to ...

Page 148

CAP_EDGE_B [1:0] CAP_EDGE_A Timer Input Capture Value A Register—Low Byte The Timer x Input Capture Value A Register—Low Byte (see byte of the capture value for external input A. For Timer 1, the external input is IC0. For Timer ...

Page 149

Timer Input Capture Value A Register—High Byte The Timer x Input Capture Value A Register—High Byte (see byte of the capture value for external input A. For Timer 1, the external input is IC0. For Timer IC2. ...

Page 150

Timer Input Capture Value B Register—High Byte The Timer x Input Capture Value B Register—High Byte (see byte of the capture value for external input B. For Timer 1, the external input is IC0. For Timer IC3. ...

Page 151

OC1_INIT 2 OC0_INIT 1 MAST_MODE 0 OC_EN Timer Output Compare Control Register 2 The Timer3 Output Compare Control Register 2 (see that occurs on the output compare pins when a timer compare happens. Table 67. Timer Output Compare Control ...

Page 152

OC1_MODE [1:0] OC0_MODE Timer Output Compare Value Register—Low Byte The Timer3 Output Compare x Value Register—Low Byte (see byte of the compare value for OC0–OC3. Table 68. Compare Value Register—Low Byte TMR3_OC1_L = 0084h, TMR3_OC2_L = 0086h, TMR3_OC3_L = ...

Page 153

Timer Output Compare Value Register—High Byte The Timer3 Output Compare x Value Register—High Byte (see byte of the compare value for OC0–OC3. Table 69. Compare Value Register—High Byte TMR3_OC1_H = 0085h, TMR3_OC2_H = 0087h, TMR3_OC3_H = 0089h) Bit Reset CPU ...

Page 154

Timer 3 16-Bit Binary Downcounter Timer 3 Count Value Clock Input Figure 30. Multi-PWM Simplified Block Diagram Setting TMR3_PWM_CTL1[MPWM_EN enables Multi-PWM mode. The TMR3_PWM_CTL1 register bits enable the 4 individual PWM generators by adjusting settings according to the ...

Page 155

The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally enabled by setting TMR3_PWM_CTL1[PAIR_EN The individual PWM generators must be enabled for the associated inverted PWM signals to be output. For each of the 4 PWM generators, ...

Page 156

Table 71. Example: Multi-PWM Addressing Parameter Timer Reload Value PWM0 rising edge PWM0 falling edge PWM1 rising edge PWM1 falling edge PWM enable PWM0 enable PWM1 enable Multi-PWM enable Prescaler Divider = 4 PWM nonoverlapping delay = 0 TMR3_PWM_CTL2[PWM_DLY] PWM ...

Page 157

The PWM generator holds the current output state until the counter reloads and cycles through to the appropriate edge transition value again. In effect, an entire cycle of the PWM ...

Page 158

PWM0 Signal PADR0 PWM0 Signal PADR4 Figure 33. PWM AND/OR Gating Functional Diagram If you enable the OR function on all PWM outputs and PADR0 is set to 1, then the PWM0 output on PA0 is forced High. Similarly, if ...

Page 159

The PWM delay feature is illustrated in Figure 34 with associated addressing listed in Note: ...

Page 160

Multi-PWM Power-Trip Mode When enabled, the Multi-PWM power-trip feature forces the enabled PWM outputs to a predetermined state when an interrupt is generated from an external source via IC0, IC1, IC2, or IC3. One or multiple external interrupt sources are ...

Page 161

Multi-PWM Control Registers Pulse-Width Modulation Control Register 1 The PWM Control Register 1 (see Table 73. PWM Control Register 1 Bit Reset CPU Access Note: R/W = Read/Write. Bit Position 7 PAIR_EN 6 PT_EN 5 MM_EN 4 pwm3_en 3 pwm2_en ...

Page 162

Pulse-Width Modulation Control Register 2 The PWM Control Register 2 (see and edge delay functions. Table 74. PWM Control Register 2 Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:6] AON_EN [5:4] AO_EN PS027001-0707 Table 74) controls pulse-width ...

Page 163

PWM_DLY PS027001-0707 No delay between falling edge of PWM (PWM) and rising 0000 edge of PWM (PWM) Delay of 1 SCLK periods between falling edge of PWM 0001 (PWM) and rising edge of PWM (PWM) Delay of 2 SCLK ...

Page 164

Pulse-Width Modulation Control Register 3 The PWM Control Register 3 (see functionality. Table 75. PWM Control Register 3 Bit Reset CPU Access Note: R/W = Read/Write Read only. Bit Position Value 0 7 PT_IC3_EN PT_IC2_EN ...

Page 165

Pulse-Width Modulation Rising Edge—Low Byte A parallel 16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs when software initiates a Write to TMR3_PWMxR_L. The register is described in Table 76. Table 76. PWMx Rising-Edge Register—Low Byte TMR3_PWM1R_L = 007Eh, TMR3_PWM2R_L = 0080h, TMR3_PWM3R_L ...

Page 166

Pulse-Width Modulation Falling Edge—Low Byte A parallel 16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs when software initiates a Write to TMR3_PWMxF_L. The register is detailed in Table 78. PWMx Falling-Edge Register—Low Byte TMR3_PWM1F_L = 0086h, TMR3_PWM2F_L = 0088h, TMR3_PWM3F_L = 008Ah) ...

Page 167

Real-Time Clock Real-Time Clock Overview The Real-Time Clock (RTC) maintains time by keeping count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour format. The format for all count and alarm registers is ...

Page 168

Real-Time Clock Alarm The clock is programmed to generate an alarm condition when the current count matches the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and day-of-the-week. Each alarm is independently enabled. To generate an alarm ...

Page 169

Write values to the RTC count registers to set the current time • Write values to the RTC alarm registers to set the appropriate alarm conditions • Write to RTC_CTRL to clear RTC_UNLOCK; clearing the RTC_UNLOCK bit resets and ...

Page 170

Real-Time Clock Minutes Register This register contains the current minutes count. The value in the RTC_MIN register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or ...

Page 171

Real-Time Clock Hours Register This register contains the current hours count. The value in the RTC_HRS register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or ...

Page 172

Real-Time Clock Day-of-the-Week Register This register contains the current day-of-the-week count. The RTC_DOW register begins counting at . The value in the RTC_DOW register is unchanged by a RESET. The 01h current setting of BCD_EN determines whether the value in ...

Page 173

Real-Time Clock Day-of-the-Month Register This register contains the current day-of-the-month count. The RTC_DOM register begins counting at . The value in the RTC_DOM register is unchanged by a RESET. The 01h current setting of BCD_EN determines whether the values in ...

Page 174

Real-Time Clock Month Register This register contains the current month count. The RTC_MON register begins counting at . The value in the RTC_MON register is unchanged by a RESET. The current setting 01h of BCD_EN determines whether the values in ...

Page 175

Real-Time Clock Year Register This register contains the current year count. The value in the RTC_YR register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or ...

Page 176

Real-Time Clock Century Register This register contains the current century count. The value in the RTC_CEN register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or ...

Page 177

Real-Time Clock Alarm Seconds Register This register contains the alarm seconds value. The value in the RTC_ASEC register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) ...

Page 178

Real-Time Clock Alarm Minutes Register This register contains the alarm minutes value. The value in the RTC_AMIN register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) ...

Page 179

Real-Time Clock Alarm Hours Register This register contains the alarm hours value. The value in the RTC_AHRS register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) ...

Page 180

Real-Time Clock Alarm Day-of-the-Week Register This register contains the alarm day-of-the-week value. The value in the RTC_ADOW register is unchanged by a RESET. The current setting of BCD_EN determines whether the value in this register is binary (BCD_EN = 0) ...

Page 181

Real-Time Clock Alarm Control Register This register contains control bits for the Real-Time Clock. The RTC_ACTRL register is cleared by a RESET. See Table 92. Real-Time Clock Alarm Control Register Bit 7 Reset 0 CPU Access R Note ...

Page 182

If the power-line frequency option is selected, the prescale value is set by the FREQ_SEL bit, and the 32 kHz oscillator is disabled. See Table 93. Real-Time Clock Control Register Bit 7 Reset X CPU Access R Note: X ...

Page 183

Universal Asynchronous Receiver/Transmitter The UART module implements all of the logic required to support the asynchronous com- munications protocol. The module also implements two separate 16-byte-deep FIFOs for both transmission and reception. A block diagram of the UART is illustrated ...

Page 184

UART Functional Description The UART Baud Rate Generator (BRG) creates the clock for the serial transmit and receive functions. The UART module supports all of the various options in the asynchro- nous transmission and reception protocol including: • ...

Page 185

UARTx_LCTL register. When enabled, an interrupt is generated after the final protocol bit is transmitted which the CPU resets by loading data into the UARTx_THR register. The TxD output is ...

Page 186

UART Interrupts There are six different sources of interrupts from the UART. The six sources of interrupts are: • Transmitter (two different interrupts) • Receiver (three different interrupts) • Modem status UART Transmitter Interrupt A Transmitter Hold Register Empty interrupt ...

Page 187

An interrupt due to one of the above conditions is cleared when the UARTx_LSR register is read. In case of FIFO mode, a line status interrupt is generated only after the received byte with an error reaches the top of ...

Page 188

When the application makes this determination, it writes the transmit data bytes to the UARTx_THR register. The number of bytes that the application writes depends on whether or not the FIFO is enabled. If the FIFO is enabled, ...

Page 189

UARTx_LSR register before reading the UARTx_RBR register to determine that there is no error in the received data. To control and check modem status, the application sets up the modem by writing to the UARTx_MCTL register and reading the UARTx_MSR ...

Page 190

BRG Control Registers UART Baud Rate Generator Register—Low and High Bytes The registers hold the Low and High bytes of the 16-bit divisor count loaded by the CPU for UART baud rate generation. The 16-bit clock divisor value is returned ...

Page 191

Table 95. UART Baud Rate Generator Register—High Bytes UART1_BRG_H = 00D1h) Bit Reset CPU Access R/W Note Read only; R/W = Read/Write. Bit Position Value [7:0] 00h–FFh UART_BRG_H UART Registers After a system reset, all UART registers are ...

Page 192

Table 96. UART Transmit Holding Registers Bit 7 Reset X CPU Access W Note Write Only. Bit Position Value Description [7:0] 00h–FFh Transmit data byte UART Receive Buffer Register The bits in this register reflect ...

Page 193

Table 98. UART Interrupt Enable Registers Bit Reset CPU Access R/W Note: R/W = Read/Write. Bit Position Value Description [7:5] 000 Reserved 0 Transmission complete interrupt is disabled 4 Transmission complete interrupt is generated when both the transmit hold TCIE ...

Page 194

UART Interrupt Identification Register The Read Only UARTx_IIR register allows you to check whether the FIFO is enabled and the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL registers. See Table 99 Table 99. UART ...

Page 195

UART FIFO Control Register This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR registers. See Table Table 101. UART FIFO Control ...

Page 196

Bit Position Value Description 0 FIFOs are not used. Receive and transmit FIFOs are used–You must clear the 0 FIFO logic using bits 1 and 2. First enable the FIFOs by setting FIFOEN 1 bit then enable ...

Page 197

Bit Position Value Description Even Parity Select Use odd parity for transmit and receive. The total number of 1 bits in the transmit 0 data plus parity bit is odd. Used as SPACE bit in Multidrop Mode. See page 189 ...

Page 198

Table 104. Parity Select Definition for Multidrop Communications (Continued) Multidrop Mode 1 1 Note: *In Multidrop Mode, EPS resets to 0 after the first character is sent. PS027001-0707 Even Parity Select Parity Type 0 space 1* mark Universal Asynchronous Receiver/Transmitter ...

Page 199

UART Modem Control Register This register is used to control and check the modem status. See Table 105. UART Modem Control Registers Bit 7 Reset 0 CPU Access R Note Read Only; R/W = Read/Write. Bit Position Value ...

Page 200

Bit Position Value Description Request to Send 1 In normal operation, the RTS output port is the inverse of this 0–1 RTS bit. In LOOP BACK mode, this bit is connected to the CTS bit in the UART Status Register. ...

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