EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 106

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
PS027001-0707
eZ80 Core
Interface
System Clock
Flash Memory Overview
Reading Flash Memory
The eZ80F91 device includes a Flash memory controller that automatically converts
standard CPU Read and Write cycles to the specific protocol required for the Flash
memory array. As such, standard memory Read and Write instructions access the Flash
memory array as if it is internal RAM. The controller also supports I/O access to the Flash
memory array, in effect presenting it as an indirectly addressable bank of I/O registers.
These access methods are also supported via the ZDI and OCI™ interfaces.
In addition, eZ80AcclaimPlus!™ Flash Microcontrollers support a Flash Read–While–
Write methodology. In other words, the eZ80 CPU continues to read and execute code
from an area of Flash memory when a nonconflicting area of Flash memory is being pro-
grammed.
The Flash memory controller contains a frequency divider, a Flash register interface, and a
Flash control state machine. A simplified block diagram of the Flash controller is
illustrated in
The main Flash memory array is read using both memory and I/O operations. As an auxil-
iary storage area, the information page is only accessible via I/O operations. In all cases,
Wait states are automatically inserted to allow for read access time.
ADDR
D
OUT
17
8
Registers
Figure 24. Flash Memory Block Diagram
Figure
8-bit downcounter
Control
Flash
Clock Divider
24.
Machine
Flash
State
FADDR
FD
FCNTL
MAIN_INFO
CPUD
FLASH_IRQ
IN
OUT
17
8
9
8
Product Specification
512 bytes
256 KB
Flash
+
eZ80F91 ASSP
Flash Memory
FD
OUT
8
98

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