EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 109

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

eZ80F91 ASSP
Product Specification
101
without first erasing it. Otherwise, the burden is on software to ensure that the 31 ms
maximum cumulative programming time between erases is not exceeded for a row.
Memory Write
A single-byte memory Write operation uses the address bus and data bus of the eZ80F91
device for programming a single data byte to Flash memory. While the CPU executes a
Load instruction, the Flash controller asserts the internal WAIT signal to stall the CPU
until the Write is complete. A single-byte Write takes between 66 µs and 85 µs to
complete. Programming an entire row using memory Writes therefore takes no more than
21.8 ms. This duration of time does not include time required by the CPU to transfer data
to the registers, which is a function of the instructions employed and the system clock
frequency.
The memory Write function does not support multibyte row programming. Because mem-
ory Writes are self-timed, they are performed back-to-back without requiring polling or
interrupts.
Erasing Flash Memory
Erasing bytes in Flash memory returns them to a value of
. Both the MASS and PAGE
FFh
ERASE operations are self-timed by the Flash controller, leaving the CPU free to execute
other operations in parallel. The DONE status bit in the Flash Interrupt Control Register
are polled by software or used as an interrupt source to signal completion of an Erase oper-
ation. If the CPU attempts to access Flash memory while an erase is in progress, the Flash
controller forces a wait state until the Erase operation is completed.
Mass Erase
Performing a MASS ERASE operation on Flash memory erases all bits contained in the
main Flash memory array. The information page remains unaffected unless the
FLASH_PAGE register bit 7(INFO_EN) is set. This self-timed operation takes
approximately 200 ms to complete.
Page Erase
The smallest erasable unit in Flash memory is a page. The pages to be erased, whether they
are the 128 main Flash memory pages or the information page, are determined by the set-
ting of the FLASH_PAGE register. This self-timed operation takes approximately 10 ms to
complete.
PS027001-0707
Flash Memory