EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 113

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Flash Control Register
The Flash Control register enables or disables memory access to Flash memory. I/O access
to the Flash control registers and to Flash memory is still possible while Flash memory
space access is disabled.
The minimum access time of internal Flash memory is 60 ns. The Flash Control Regis-
ter must be configured to provide the appropriate number of wait states based on the sys-
tem clock frequency of the eZ80F91 device. Because the maximum SCLK frequency is
50 MHz (20 ns), the default on RESET is for four Wait states to be inserted for Flash
memory access (Flash memory access + one eZ80
80 ns ÷ 20 ns = 4 Wait states). See
Table 38. Flash Control Register
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit Position
[7:5]
FLASH_WAIT
[4]
[3]
FLASH_EN
[2:0]
Value Description
000
001
010
011
100
101
110
111
0
0
1
000
0 wait states are inserted when the Flash is active.
1 wait state is inserted when the Flash is active.
2 wait states are inserted when the Flash is active.
3 wait states are inserted when the Flash is active.
4 wait states are inserted when the Flash is active.
5 wait states are inserted when the Flash is active.
6 wait states are inserted when the Flash is active.
7 wait states are inserted when the Flash is active.
Reserved.
Flash memory access is disabled.
Flash memory access is enabled.
Reserved.
R/W
7
1
R/W
Table
6
0
(FLASH_CTRL = 00F8h)
38.
R/W
5
0
®
Bus Cycle = 60 ns + 20 ns = 80 ns;
R
4
0
R/W
3
1
Product Specification
R
2
0
eZ80F91 ASSP
R
1
0
Flash Memory
R
0
0
105