EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 114

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Flash Frequency Divider Register
The 8-bit frequency divider allows the programming of Flash memory over a range of
system clock frequencies. Flash is programmed with system clock frequencies ranging
from 154 kHz to 50 MHz. The Flash controller requires an input clock with a period that
falls within the range of 5.1−6.5 µs. The period of the Flash controller clock is set in the
Flash Frequency Divider Register. Writes to this register is allowed only after it is
unlocked via the FLASH_KEY register. The Flash Frequency Divider Register value
required versus the system clock frequency is displayed in
frequencies outside of the ranges shown are not supported. Register values for the Flash
Frequency Divider are displayed in
Table 39. Flash Frequency Divider Values
Table 40. Flash Frequency Divider Register
System Clock Frequency
154–196 kHz
308–392 kHz
462–588 kHz
616 kHz–50 MHz
Note: *The CEILING function rounds fractional values up to the next whole number. For example,
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes
Bit Position
[7:0]
FLASH_FDIV
CEILING(3.01) is 4.
Value
01h–FFh Divider value for generating the required 5.1-6.5 µs Flash
R/W*
7
0
Description
controller clock period.
Flash Frequency Divider Value
1
2
3
CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*
R/W*
Table
6
0
40.
R/W*
5
0
R/W*
(FLASH_FDIV = 00F9h)
4
0
R/W*
Table
3
0
Product Specification
39. System clock
R/W*
2
0
eZ80F91 ASSP
R/W*
1
0
Flash Memory
R/W
0
1
106