EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 135

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
The following is a list of the special features for each timer:
•
•
•
•
Timer 3 consists of three specialty modes. Each of these modes are enabled using bits in
their respective control registers (TMR3_CAP_CTL, TMR3_OC_CTL1,
TMR3_PWM_CTL1). When PWM mode is enabled, the OUTPUT COMPARE and
INPUT CAPTURE modes are not available. This instance is due to address space sharing
requirements. However, INPUT CAPTURE and OUTPUT COMPARE modes run
simultaneously.
Timers with specialty modes offer multiple ways to generate an interrupt. When the inter-
rupt controller services a timer interrupt, the software must read the timers interrupt iden-
tification register (TMRx_IIR) to determine the causes for an interrupt request. This
register is cleared each time it is read, allowing subsequent events to be identified without
interference from prior events.
Event Counter
When a timer is configured to take its input from a port input pin (ECx), it functions as an
event counter. For event counting, the clock prescaler is automatically bypassed and edges
(events) cause the timer to decrement. You must select the rising or the falling edge for
counting. Also, the port pins must be configured as inputs.
Input sampling on the port pins results in the counter being updated on the third rising
edge of the system clock after the edge event occurs at the port pin. Due to sampling, the
frequency of the event input is limited to one-half the system clock frequency under ideal
conditions. In practice, the event frequency must be less than this value due to duty cycle
variation and system clock jitter.
This EVENT COUNT mode is identical to basic timer operation, except for the clock
source. Therefore, interrupts are managed in the same manner.
Timer 0
–
Timer 1
–
–
Timer 2
–
Timer 3
–
–
–
No special functions
One event counter (EC0)
Two input captures (IC0 and IC1)
One event counter (EC1)
Two input captures (IC2 and IC3)
Four output compares (OC0, OC1, OC2, and OC3)
Four PWM outputs (PWM0, PWM1, PWM2, and PWM3)
Programmable Reload Timers
Product Specification
eZ80F91 ASSP
127