EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 143

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Timer Interrupt Identification Register
The TImer x Interrupt Identification Register (see
that the CPU determines the cause of a timer interrupt. This register is cleared by a CPU
Read.
Table 56. Timer Interrupt Identification Register
0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h)
Bit
Reset
CPU Access
Note: R = Read only;
Bit
Position
7
6
OC3
5
OC2
4
OC1
3
OC0
2
ICB
1
ICA
0
EOC
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Unused.
Output compare, OC3, does not occur.
Output compare, OC3, occurs.
Output compare, OC2, does not occur.
Output compare, OC2, occurs.
Output compare, OC1, does not occur.
Output compare, OC1, occurs.
Output compare, OC0, does not occur.
Output compare, OC0, occurs.
Input capture, ICB, does not occur.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICB, occurs.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICA, or PWM power trip does not occur.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
Input capture, ICA, or PWM power trip occurs.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
End-of-count does not occur.
End-of-count occurs.
R
7
0
R
6
0
R
5
0
Table
R
4
0
56) is used to flag timer events so
(TMR0_IIR = 0062h, TMR1_IIR =
R
3
0
Programmable Reload Timers
Product Specification
R
2
0
eZ80F91 ASSP
R
1
0
R
0
0
135