EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 148

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Timer Input Capture Value A Register—Low Byte
The Timer x Input Capture Value A Register—Low Byte (see
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.
Table 62. Timer Input Capture Value Register A—Low Byte
006Bh, TMR3_CAPA_L = 007Ch)
[3:2]
CAP_EDGE_B
[1:0]
CAP_EDGE_A
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR
x
_CAPA_L
00
01
10
11
00
01
10
11
Value
00h–FFh
R
7
0
Disable capture on ICB.
Enable capture only on the falling edge of ICB.
Enable capture only on the rising edge of ICB.
Enable capture on both edges of ICB.
Disable capture on ICA.
Enable capture only on the falling edge of ICA
Enable capture only on the rising edge of ICA.
Enable capture on both edges of ICA.
Description
These bits represent the Low byte of the 2-byte capture
value, {TMR
bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
R
6
0
x
_CAPA_H[7:0], TMR
R
5
0
R
4
0
R
3
0
Table
Programmable Reload Timers
Product Specification
x
_CAPA_L[7:0]}. Bit 7 is
62) stores the Low
R
2
0
(TMR1_CAPA_L =
eZ80F91 ASSP
R
1
0
R
0
0
140