EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 164

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Pulse-Width Modulation Control Register 3
The PWM Control Register 3 (see
functionality.
Table 75. PWM Control Register 3
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read only.
Bit
Position
7
PT_IC3_EN
6
PT_IC2_EN
5
PT_IC1_EN
4
PT_IC0_EN
3
PT_TRI
2
PT_LVL
1
PT_LVL_N
0
PTD
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Power trip disabled on IC3.
Power trip enabled on IC3.
Power trip disabled on IC2.
Power trip enabled on IC2.
Power trip disabled on IC1.
Power trip enabled on IC1.
Power trip disabled on IC0.
Power trip enabled on IC0.
All PWM trip levels are open-drain
All PWM trip levels are defined by PT_LVL and PT_LVL_N
After power trip, PWMx outputs are set to one.
After power trip, PWMx outputs are set to zero.
After power trip, PWMx outputs are set to one.
After power trip, PWMx outputs are set to zero.
Power trip has been cleared.
This bit is set after power trip event.
R/W
7
0
R/W
Table
6
0
75) is used to configure the PWM power trip
(PWM_CTL3 = 007Bh)
R/W
5
0
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 ASSP
R/W
1
0
R
0
0
156