EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 181

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 92. Real-Time Clock Alarm Control Register
PS027001-0707
Bit
Reset
CPU Access
Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write
Bit Position
[7:4]
3
ADOW_EN
2
AHRS_EN
1
AMIN_EN
0
ASEC_EN
Real-Time Clock Alarm Control Register
This register contains control bits for the Real-Time Clock. The RTC_ACTRL register is
cleared by a RESET. See
Real-Time Clock Control Register
This register contains control and status bits for the Real-Time Clock. Some bits in the
RTC_CTRL register are cleared by a RESET. The ALARM bit flag and associated inter-
rupt (if INT_EN is enabled) are cleared by reading this register. The ALARM bit flag is
updated by clearing (locking) the RTC_UNLOCK bit or by an increment of the RTC
count. Writing to the RTC_CTRL register also resets the RTC count prescaler allowing the
RTC to be synchronized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
mode. This bit is checked after RESET to determine if a sleep-mode recovery is caused by
the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register.
Setting the BCD_EN bit causes the RTC to use binary-coded decimal
all registers including the alarm set points.
The CLK_SEL and FREQ_SEL bits select the RTC clock source. If the 32 KHz crystal
option is selected, the oscillator is enabled and the internal prescaler is set to divide by
Value Description
0000
0
1
0
1
0
1
0
1
Reserved.
The day-of-the-week alarm is disabled.
The day-of-the-week alarm is enabled.
The hours alarm is disabled.
The hours alarm is enabled.
The minutes alarm is disabled.
The minutes alarm is enabled.
The seconds alarm is disabled.
The seconds alarm is enabled.
R
7
0
R
6
0
Table
R
5
0
92.
R
4
0
R/W
(RTC_ACTRL = 00ECh)
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
(
BCD) counting in
eZ80F91 ASSP
Real-Time Clock
173