EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 19

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
70
71
72
73
74
BGA
Pin No Symbol
M10
L10
M11
M12
L12
TDO
TRST
V
PD0
TxD0
IR_TxD
PD1
RxD0
IR_RxD
SS
Function
JTAG Test
GPIO Port D
GPIO Port D
Data Out
JTAG Reset
Ground
UART
Transmit Data
IrDA Transmit
Data
Receive Data
IrDA Receive
Data
Signal Direction Description
Output
Schmitt-trigger
input, Active Low
Bidirectional
Output
Output
Bidirectional
Input
Input
JTAG data output pin.
JTAG reset input pin.
Ground.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually
as an interrupt input. Each Port D
pin, when programmed as output is
selected to be an open-drain or
open-source output. Port D is
multiplexed with one UART.
This pin is used by the UART to
transmit asynchronous serial data.
This signal is multiplexed with PD0.
This pin is used by the IrDA
encoder/decoder to transmit serial
data. This signal is multiplexed with
PD0.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually
as an interrupt input. Each Port D
pin, when programmed as output is
selected to be an open-drain or
open-source output. Port D is
multiplexed with one UART.
This pin is used by the UART to
receive asynchronous serial data.
This signal is multiplexed with PD1.
This pin is used by the IrDA
encoder/decoder to receive serial
data. This signal is multiplexed with
PD1.
Product Specification
Architectural Overview
eZ80F91 ASSP
11