EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 191

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 95. UART Baud Rate Generator Register—High Bytes
UART1_BRG_H = 00D1h)
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_H
UART Registers
After a system reset, all UART registers are set to their default values. Any Writes to unused
registers or register bits are ignored and reads return a value of 0. For compatibility with
future revisions, unused bits within a register must always be written with a value of 0.
Read/Write attributes, reset conditions, and bit descriptions of all of the UART registers are
provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The Transmit FIFO is mapped at this address.
You can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See
Value
00h–FFh
Table 96
R/W
7
0
Description
These bits represent the High byte of the 16-bit BRG divider value. The
complete BRG divisor value is returned by {UART_BRG_H,
UART_BRG_L}.
on page 184.
R/W
6
0
R/W
5
0
R/W
4
0
Universal Asynchronous Receiver/Transmitter
R/W
(UART0_BRG_H = 00C1h,
3
0
R/W
Product Specification
2
0
eZ80F91 ASSP
R/W
1
0
R/W
0
0
183