EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 195

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 101. UART FIFO Control Registers
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:6]
TRIG
[5:3]
2
CLRTxF
1
CLRRxF
UART FIFO Control Register
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See
Value
00
01
10
11
000b
0
1
0
1
Description
Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
Reserved—must be 000b.
Transmit Disable. This register bit works differently than the
standard 16550 UART. This bit must be set to transmit data.
When it is reset the transmit FIFO logic is reset along with the
associated transmit logic to keep them in sync. This bit is now
persistent–it does not self clear and it must remain at 1 to
transmit data.
Transmit Enable
Receive Disable. This register bit works differently than the
standard 16550 UART. This bit must be set to receive data.
When it is reset the receive FIFO logic is reset along with the
associated receive logic to keep them in sync and avoid the
previous version’s lookup problem. This bit is now persistent–it
does not self clear and it must remain at 1 to receive data.
Receive Enable
W
7
0
Table
W
6
0
101.
W
5
0
(UART0_FCTL = 00C2h, UART1_FCTL = 00D2h)
W
4
0
W
3
0
Universal Asynchronous Receiver/Transmitter
W
2
0
W
1
0
Product Specification
W
0
0
eZ80F91 ASSP
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