EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 196

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 102. UART Line Control Registers
PS027001-0707
Bit
Position
0
FIFOEN
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position Value
7
DLAB
6
SB
5
FPE
0
1
0
1
0
1
UART Line Control Register
This register is used to control the communication control parameters. See
Table 103
Value
0
1
Description
Access to the UART registers at I/O addresses C0h, C1h, D0h and D1h is enabled.
Access to the Baud Rate Generator registers at I/O addresses C0h, C1h, D0h and
D1h is enabled.
Do not send a BREAK signal.
Send Break
UART sends continuous zeroes on the transmit output from the next bit boundary.
The transmit data in the transmit shift register is ignored. After forcing this bit High,
the
0, the transmit FIFO is cleared. Any new data written to the transmit FIFO during a
break must be written only after the THRE bit of UARTx_LSR register goes High.
This new data is transmitted after the UART recovers from the break. After the break
is removed, the UART recovers from the break for the next BRG edge.
Do not force a parity error.
Force a parity error. When this bit and the parity enable bit (pen) are both 1, an
incorrect parity bit is transmitted with the data byte.
T
x
Description
FIFOs are not used.
Receive and transmit FIFOs are used–You must clear the
FIFO logic using bits 1 and 2. First enable the FIFOs by setting
bit 0 to 1 then enable the receiver and transmitter by setting
bits 1 and 2.
on page 189.
D
output is 0 only after the bit boundary is reached. Just before forcing
R/W
7
0
R/W
6
0
(UART0_LCTL = 00C3h, UART1_LCTL = 00D3h)
R/W
5
0
R/W
4
0
Universal Asynchronous Receiver/Transmitter
R/W
3
0
R/W
2
0
Product Specification
R/W
1
0
eZ80F91 ASSP
Table 102
R/W
0
0
T
x
D
and
to
188