EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 206

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
UART_TxD
Baud Rate
Transmit
Receive
IR_TxD
7-clock
Clock
delay
IrDA specifications. The UART must be enabled to use the endec. For more information on
the UART and its BRG, see
The data to be transmitted via the IR transceiver is the data sent to UART0. The UART
transmit signal, TxD, and Baud Rate Clock are used by the endec to generate the
modulation signal, IR_TxD, that drives the infrared transceiver. Each UART bit is 16
clocks wide. If the data to be transmitted is a logical 1 (High), the IR_TxD signal remains
Low (0) for the full 16-clock period. If the data to be transmitted is a logical 0, a 3-clock
High (1) pulse is output following a 7-clock Low (0) period. Following the 3-clock High
pulse, a 6-clock Low pulse completes the full 16-clock data period. Data transmission is
illustrated in
disabled by clearing the IR_RxEN bit in the IR_CTL reg to 0 to prevent transmitter-to-
receiver crosstalk.
Data received from the IR transceiver via the IR_RxD signal is decoded by the endec and
passed to the UART. The IR_RxEN bit in the IR_CTL register must be set to enable the
receiver decoder. The IrDA serial infrared (SIR) data format uses half duplex communica-
tion. Therefore, the UART must not be allowed to transmit while the receiver decoder is
enabled. The UART Baud Rate Clock is used by the endec to generate the demodulated
signal, RxD, that drives the UART. Each UART bit is 16 clocks wide. If the data to be
received is a logical 1 (High), the IR_RxD signal remains High (1) for the full 16-clock
Start Bit = 0
16-clock
period
3-clock
pulse
Figure
Figure 38. Infrared Data Transmission
38. During data transmission, the IR receive function must be
Data Bit 0 = 1
Universal Asynchronous Receiver/Transmitter
Data Bit 1 = 0
Data Bit 2 = 1
Product Specification
Infrared Encoder/Decoder
Data Bit 3 = 1
eZ80F91 ASSP
on page 175.
198