EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 215

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
PS027001-0707
SPI Baud Rate Generator
Data Transfer Procedure with SPI Configured as a Master
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI inter-
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault Flag is cleared to 0.
Write Collision
The write collision flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to write
to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing the
WCOL bit is performed by reading SPI_SR with the WCOL bit set to 1.
The SPI’s Baud Rate Generator (BRG) creates a lower frequency clock from the high-fre-
quency system clock. The BRG output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI’s BRG consists of a 16-bit downcounter, two 8-bit registers, and associated
decoding logic. The BRG’s initial value is defined by the two BRG Divisor Latch registers
{SPI_BRG_H, SPI_BRG_L}. At the rising edge of each system clock, the BRG decre-
ments until it reaches the value
reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate
the end of the count.
The SPI Data Rate is calculated using the following equation:
Upon RESET, the 16-bit BRG divisor value resets to
a Master, the BRG divisor value must be set to a value of
is operating as a Slave, the BRG divisor value must be set to a value of
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.
The following list describes the procedure for transferring data from a master SPI device
to a slave SPI device.
rupt is generated.
SPI Data Rate (bits/s)
=
0001h
2 X SPI Baud Rate Generator Divisor
System Clock Frequency
. On the next system clock rising edge, the BRG
0002h
0003h
. When the SPI is operating as
Product Specification
or greater. When the SPI
Serial Peripheral Interface
0004h
eZ80F91 ASSP
or greater.
207

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