EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 219

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 115. SPI Status Register
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
SPI Status Register
The SPI Status Read Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data over
SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly into
the shift register for transmission. A Write to this register within an SPI device configured
as a master initiates transmission of the byte of the data loaded into the register. At the
completion of transmitting a byte of data, the SPI Flag (SPI_SR[7]) is set to 1 in both the
master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the SPI
Receive Buffer Read Only register. See
Value Description
0
1
0
1
0
0
1
0000
Table
115.
SPI data transfer is not finished.
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit Flag is cleared to 0
by a Read of the SPI_SR registers.
Reserved.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit Flag is
cleared to 0 by a Read of the SPI_SR register.
Reserved.
R
7
0
(SPI_SR = 00BBh)
R
6
0
R
5
0
R
4
0
Table 116
R
3
0
on page 212.
R
2
0
R
1
0
Product Specification
Serial Peripheral Interface
R
0
0
eZ80F91 ASSP
211