EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 236

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
PS027001-0707
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing 0 to the STA bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I
ates as if a STOP condition is received, but no STOP condition is transmitted. If both STA
and STP bits are set, the I
mode), then transmits the START condition. The STP bit is cleared to 0 automatically.
Writing a 0 to this bit produces no effect.
The I
I
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I
the Low period of the I
When a 0 is written to IFLG, the interrupt is cleared and the I
When the I
acknowledge clock pulse on the I
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte in the
I
block enters the
to its slave address unless AAK is set to 1. See
2
2
C states is entered. The only state that does not set the IFLG bit is state
C_DR register is assumed to be the final byte. After this byte is transmitted, the I
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received.
The general call address is received and the General Call Enable bit in I
to 1.
A data byte is received while in MASTER or SLAVE modes.
2
C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
2
C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during the
C8h
2
C bus. If the STP bit is set to 1 in SLAVE mode, the I
state, then returns to an idle state. The I
2
C bus clock line is stretched and the data transfer is suspended.
2
C block first transmits the STOP condition (if in MASTER
2
C bus if:
Table 127
on page 229.
2
2
C module does not respond
C clock line is released.
Product Specification
I
2
C Serial I/O Interface
eZ80F91 ASSP
F8h
2
C module oper-
2
C_SAR is set
. If IFLG is
2
C
2
C,
228

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