EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 246

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated
in
ZCL as illustrated in
the ninth cycle and holds the ZCL signal High.
ZDI Single-Bit Byte Separator
Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a
new ZDI command, the single-bit byte separator must be High (logical 1) to allow for a
new ZDI START command to be sent. For all other cases, the single-bit byte separator is
either Low (logical 0) or High (logical 1). When ZDI is configured to allow the CPU to
ZDA
ZCL
Figure
ZDA
ZCL
50. Data is shifted out during a Read from the ZDI block on the falling edge of
Start Signal
Start Signal
Figure
51. When an operation is completed, the master stops during
Figure 50. ZDI Write Timing
Figure 51. ZDI Read Timing
ZDI Data In
(Write)
ZDI Data Out
(Read)
ZDI Data In
(Write)
Product Specification
ZDI Data Out
(Read)
Zilog Debug Interface
eZ80F91 ASSP
238