EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 247

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
ZDA
ZCL
ZDI Register Addressing
START
Signal
accept external bus requests, the single-bit byte separator must be Low (logical 0) during
all ZDI commands. This Low value indicates that ZDI is still operating and is not ready to
relinquish the bus. The CPU does not accept the external bus requests until the single-bit
byte separator is a High (logical 1). For more information on accepting bus requests in
ZDI DEBUG mode, see
Following a START signal the ZDI master must output the ZDI register address. All data
transfers with the ZDI block use special ZDI registers. The ZDI control registers that
reside in the ZDI register address space must not be confused with the eZ80F91 device
peripheral registers that reside in the I/O address space.
Many locations in the ZDI control register address space are shared by two registers—one
for Read Only access and one for Write Only access. For example, a Read from ZDI regis-
ter address
tion,
break points.
The format for a ZDI address is seven bits of address, followed by one bit for Read or
Write control, and completed by a single-bit byte separator. The ZDI executes a Read or
Write operation depending on the state of the R/W bit (0 = Write, 1 = Read). If no new
START command is issued at completion of the Read or Write operation, the operation is
repeated. This allows repeated Read or Write operations without having to resend the ZDI
command. A START signal must follow to initiate a new ZDI command.
trates the timing for address Writes to ZDI registers.
S
00h
, stores the Low byte of one of the address match values used for generating
msb
A6
1
00h
Figure 52. ZDI Address Write Timing
returns the eZ80
A5
2
Bus Requests During ZDI Debug Mode
A4
3
ZDI Address Byte
®
Product ID Low Byte, while a Write to this same loca-
A3
4
A2
5
A1
6
A0
lsb
7
0 = WRITE
1 = READ
Product Specification
on page 242.
R/W
8
Byte Separator
START Signal
or new ZDI
Zilog Debug Interface
Single-Bit
eZ80F91 ASSP
Figure 52
0/1
9
illus-
239