EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 256

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
PS027001-0707
Bit
Position
2
ign_low_1
1
ign_low_0
0
single_step
Value Description
0
1
0
1
0
1
The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If brk_addr1 is set to 1, ZDI initiates
a break when the entire 24-bit address, ADDR[23:0],
matches the 3-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H, ZDI_ADDR1_L}.
The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If brk_addr1 is set to 1, ZDI initiates
a break when only the upper 2 bytes of the 24-bit address,
ADDR[23:8], match the 2-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H}. As a result, a break occurs anywhere
within a 256-byte page.
The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If brk_addr0 is set to 1, ZDI initiates
a break when the entire 24-bit address, ADDR[23:0],
matches the 3-byte value {ZDI_ADDR0_U,
ZDI_ADDR0_H, ZDI_ADDR0_L}.
The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If the brk_addr1 is set to 0, ZDI
initiates a break when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2 bytes value
{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a break
occurs anywhere within a 256-byte page.
ZDI single step mode is disabled.
ZDI single step mode is enabled. ZDI asserts a break
following execution of each instruction.
Product Specification
Zilog Debug Interface
eZ80F91 ASSP
248

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