EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 268

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 149. ZDI Read Memory Register
Address Space)
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
zdi_rd_mem
Note that the delay between issuing a memory read request and the return of the corre-
sponding data amount to multiple ZDI clock cycles. This delay is a function of the wait
state configuration of the memory space being accessed as well as the relative frequencies
of the ZDI clock and the system clock. If the ZDI master begins clocking the read data out
of the eZ80F91 soon after issuing the memory read request, invalid data will be returned.
Since no data-valid handshake mechanism exists in the ZDI protocol, the ZDI master must
account for expected memory read delay in some way.
A technique exists to mask this delay in almost all situations. It always reads at least two
consecutive bytes, starting one address lower than the address of interest. In this situation,
the eZ80F91 internally prefetches the data from the second address while the ZDI master
is sending the second read request. This allows enough time for the second ZDI memory
read to return valid data. The first data byte returned to the ZDI master must be discarded
since it is invalid. Memory reads of more than two consecutive bytes will also return cor-
rect data for all but the first address.
Value
00h–FFh 8-bit data Read from the memory address indicated by
R
7
0
Description
the CPU’s Program Counter. In Z80 Memory mode, 8-bit
data is transferred out from address {MBASE, PC[15:0]}.
In ADL Memory mode, 8-bit data is transferred out from
address PC[23:0].
R
6
0
R
5
0
(ZDI_RD_MEM = 20h in the ZDI Register Read Only
R
4
0
R
3
0
R
2
0
R
1
0
Product Specification
R
0
0
Zilog Debug Interface
eZ80F91 ASSP
260