EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 300

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Note:
EMAC Functional Description
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•
•
The media access control block implements 802.3x flow control functions for both trans-
mit and receive.
The MII management module provides a two-wire control/status path to the MII PHY.
Read and Write communication to and from registers within the PHY is accomplished via
the host interface.
MII PHY is a Physical Layer transceiver device; PHY does not refer to the eZ80F91 sys-
tem clock output pin, PHI.
The MII management module provides a two-wire control/status path to the MII. Read
and Write communication to and from registers within the PHY is accomplished via the
host interface.
The EMAC block implements memory, arbiter, and transmit and receive direct memory
access functions, and offers four communication modes: HALF-DUPLEX, FULL-
DUPLEX, NIBBLE, and ENDEC. In HALF-DUPLEX and FULL-DUPLEX modes,
throughput occurs at both 10 Mbps and 100 Mbps speeds. Throughput in ENDEC and
NIBBLE modes occurs at 10 Mbps. A brief description of these four modes are as follows:
10/100 Mbps HALF-DUPLEX Mode—
direction at a time; that is, one can either transmit or receive, but both cannot occur
simultaneously.
10/100 Mbps FULL-DUPLEX Mode—
the same time.
10 Mbps ENDEC Mode—
MAC. In ENDEC mode, the RxCLK and TxCLK clocks are bit clocks instead of the nor-
mal nibble clock. In NIBBLE mode, 4 bits are transferred on each clock. In ENDEC
mode, 1 bit is transferred per clock.
For more information on throughput, see
Memory
EMAC memory is the shared Ethernet memory location of the Transmit and Receive buff-
ers. This memory is broken into two parts: the Tx buffer and the Rx buffer. The Transmit
Lower Boundary Pointer Register, EmacTLBP, is the register that holds the starting
address of the Tx buffer. The Boundary Pointer Register, EmacBP, points to the start of the
Rx buffer (end of Tx buffer + 1). The Receive High Boundary Pointer Register,
FIFO buffer and DMA control blocks for transmit and receive.
802.3x media access control block.
MII interface management.
This mode affects the MII interface between the PHY and the
In this mode, data are transmitted and received at
In this mode, data are transferred only in one
EMAC and the System Clock
Ethernet Media Access Controller
Product Specification
on page 300.
eZ80F91 ASSP
292