EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 305

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
•
Figure 60
The Transmit and Receive buffers are subdivided into packet buffers of 32, 64, 128, or 256
bytes in size. The packet buffer size is set in bits 7 and 6 of the EmacBufSize register. An
Ethernet packet accommodate multiple packet buffers. First, however, a brief listing of the
contents of a typical Ethernet packet is in order. See
Table 177. Ethernet Packet Contents
At the start of each packet is a descriptor table that describes the packet. Each actual
Ethernet packet follows the descriptor table as illustrated in
Byte Range
Bytes 0–5
Bytes 6–11
Bytes 12–13
Bytes 14–n
Bytes (n+1)–(n+4)
RHBP
TLBP
Receive High Boundary Pointer (RHBP)—this register points to the end of the Receive
buffer + 1.
BP
displays the internal Ethernet shared memory.
Figure 60. Internal Ethernet Shared Memory
Contents
MAC destination address.
MAC source address.
Length/Type field.
MAC Client Data.
Frame Check Sequence.
Rx Buffer
Tx Buffer
Upper Memory Address
Lower Memory Address
Table
177.
Ethernet Media Access Controller
Figure 61
Product Specification
on page 298.
eZ80F91 ASSP
297