EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 308

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 179. Receive Descriptor Status (Continued)
PS027001-0707
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
RxLongEvent
RxPCF
RxCF
RxMcPkt
RxBcPkt
RxVLAN
RxUOpCode
RxLOOR
RxLCError
RxCodeV
RxCEvent
RxDvEvent
RxOVR
EMAC and the System Clock
Effective Ethernet throughput in any given system is dependent upon factors such as sys-
tem clock speed, network protocol overhead, application complexity, and network traffic
conditions at any given moment. The following information provides a general guideline
about the effects of system clock speed on Ethernet operation.
The eZ80F91 ASSP's EMAC block performs a synchronous function that is designed to
operate over a wide range of system clock frequencies. To understand its maximum data
Description
1 = A Long or Dropped Event occurs. A Long Event is when a packet
over 50,000 bit times occurs. A Dropped Packet occurs if the minimum
interpacket gap is not met, the preamble is not pure, and the
EmacCfg3[PUREP] bit is set, or if a preamble over 11 bytes in length is
detected and the EmacCfg3[LONGP] bit is set to 1.
1 = The packet is a pause control frame.
1 = The packet is a control frame.
1 = The packet contains a multicast address.
1 = The packet contains a broadcast address.
1 = The packet is a VLAN packet.
1 = An unsupported opcode is indicated in the opcode field of the
Ethernet packet.
1 = The Type/Length field is out of range (larger than 1518 bytes).
1 = Type/Length field is not a Type field and it does not match the
actual data byte length of the Ethernet packet. The data byte length is
the number of bytes of data in the Ethernet packet between the Type/
Length field and the FCS.
1 = A code violation is detected. The PHY asserts Rx error (RxER).
1 = A carrier event is previously seen. This event is defined as Rx error
RxER = 1, receive data valid (RxDV) = 0 and receive data (RxD) = Eh.
1 = A receive data (RxDV) event is previously seen. Indicates that the
last Receive event is not long enough to be a valid packet.
1 = A Receive overrun occurs in this packet. An overrun occurs when
all of the EMAC Receive buffers are in use and the Receive FIFO is full.
The hardware ignores all incoming packets until the EmacIStat
Register [Rx_Ovr] bit is cleared by the software. There is no indication
as to how many packets are ignored.
Ethernet Media Access Controller
Product Specification
eZ80F91 ASSP
300