EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 310

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 180. EMAC Test Register
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit
Position
7
6
TEST_FIFO
5
TxRx_SEL
4
SSTC
3
SIMR
2
FRC_OVR_ERR
1
FRC_UND_ERR
0
LPBK
EMAC Test Register
The EMAC Test Register allows test functionality of the EMAC block. Available test
modes are defined for bits [6:0]. See
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R
7
0
Description
Reserved.
FIFO test mode disabled—Normal operation.
FIFO test mode enabled.
Select the Receive FIFO when FIFO test mode is enabled.
Select the Transmit FIFO when FIFO test mode is enabled.
Normal operation.
Short Cut Slot Timer Counter. Slot time is shortened to
speed up simulation.
Normal operation.
Simulation Reset.
Normal operation.
Force Overrun error in Receive FIFO.
Normal operation.
Force Underrun error in Transmit FIFO.
Normal operation.
EMAC Transmit interface is looped back into EMAC Receive
interface.
R/W
6
0
(EMAC_ TEST = 0020h)
R/W
5
0
R/W
4
0
Table
R/W
180.
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
302