EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 316

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 186. EMAC Station Address Register (EMAC_STAD_0 = 0025h, EMAC_STAD_1 =
EMAC_STAD_5 = 002Ah)
PS027001-0707
0026h, EMAC_STAD_2 = 0027h, EMAC_STAD_3 = 0028h, EMAC_STAD_4 = 0029h,
Bit
EMAC_STAD_0 Reset
EMAC_STAD_1 Reset
EMAC_STAD_2 Reset
EMAC_STAD_3 Reset
EMAC_STAD_4 Reset
EMAC_STAD_5 Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_STAD_x
the sixth byte Destination Address (DA) field of the Receive frame. EMAC_STAD_0 is
matched against the first byte of the Receive frame, and EMAC_STAD_5 is matched
against the sixth byte of the Receive frame. Bit 0 of EMAC_STAD_0 (STAD[40]) is
matched against the first bit (Unicast/Multicast bit) of the first byte of the Receive
frame. This bit ordering is used to logically map the PE-MACMII station address as
illustrated below.
EMAC_STAD0[7:0] contains STAD[47:40]
....
....
EMAC_STAD5[7:0] contains STAD[7:0]
The second function of the EMAC Station Address registers is to provide the Source
Address (SA) field of Transmit Pause frames when these frames are transmitted by the
EMAC. EMAC_STAD_0 provides the first byte of the 6 byte SA field and
EMAC_STAD_5 provides the final byte of the SA field in order of transmission. The LSB
is the first byte sent out. The EMAC Station Address register is detailed in
Value
00h–FFh This 48-bit station address comprises {EMAC_STAD_5,
R/W
Description
EMAC_STAD_4, EMAC_STAD_3, EMAC_STAD_2,
EMAC_STAD_1, EMAC_STAD_0}.
7
0
0
0
0
0
0
R/W
6
0
0
0
0
0
0
R/W
5
0
0
0
0
0
0
R/W
4
0
0
0
0
0
0
R/W
3
0
0
0
0
0
0
R/W
2
0
0
0
0
0
0
Ethernet Media Access Controller
R/W
1
0
0
0
0
0
0
Product Specification
R/W
0
0
0
0
0
0
0
eZ80F91 ASSP
Table
186.
308