EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 321

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 193. EMAC Non-Back-To-Back IPG Register—Part 2
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
[6:0]
IPGR2
Note:
EMAC Maximum Frame Length Register—Low and High Bytes
The 16-bit field resets to
bytes. An untagged maximum size Ethernet frame (packet) is 1518 bytes. A tagged frame
adds four bytes for a total of 1522 bytes. If a shorter maximum length restriction is more
appropriate, program this field. See
The default value of 1536 bytes is large enough to cover the largest Ethernet packet, which
contains 14 bytes of Ethernet header, 1500 bytes of MAC client data, plus 4 bytes of CRC
for a total of 1518 maximum bytes. This value is also large enough to cover VLAN frames
with prepended headers up to 18 bytes.
VLAN frames have a proprietary header prepended to the Ethernet packet. Setting the
DCRCC bit in EMAC_CFG1 will exclude the first 4 bytes—the proprietary header—from
the CRC calculation. For VLAN packets, the maximum frame length is 1522, 4 more than
for normal Ethernet packets due to the 4 byte prepended header. Normal packets feature a
12 byte header before the MAC client data. For more information about this topic, refer to
Figure 3-1 of the IEEE 802.3 specification.
If a proprietary header is allowed, this field must be adjusted accordingly. For example, if
12 byte headers are prepended to frames, MAXF must be set to 1524 bytes to allow the
maximum VLAN tagged frame plus the 12 byte header. The default value of 1536 is large
enough to cover the largest Ethernet packet: 14 bytes of Ethernet header, 1500 bytes of
MAC client data, plus 4 bytes of CRC for a total of 1518 bytes maximum. It is also large
enough to cover VLAN packets with prepended headers up to 18 bytes. The following
formulas illustrate:
Ethernet Packet—
+ 1500 (MAC client data) + 4 (CRC) = 1518 bytes
Value
0
00h–7Fh This bit range is a programmable field representing the non-
Description
Reserved.
back-to-back interpacket gap.
R
7
0
R/W
6
0
Maximum frame size = normal Ethernet packet – 14 (Ethernet header)
0600h
R/W
5
0
, which represents a maximum Receive frame of 1536
R/W
Table 194
4
1
R/W
3
0
and
Table 195
R/W
(EMAC_IPGR2 = 002Fh)
2
0
R/W
Ethernet Media Access Controller
1
1
on page 314.
Product Specification
R/W
0
0
eZ80F91 ASSP
313