EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 324

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 197. EMAC Hash Table Register (EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h,
EMAC_HTBL_2 = 0035h, EMAC_HTBL_3 = 0036h, EMAC_HTBL_4 = 0037h, EMAC_HTBL_5
= 0038h, EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah)
PS027001-0707
Bit
EMAC_HTBL_0 Reset
EMAC_HTBL_1 Reset
EMAC_HTBL_2 Reset
EMAC_HTBL_3 Reset
EMAC_HTBL_4 Reset
EMAC_HTBL_5 Reset
EMAC_HTBL_6 Reset
EMAC_HTBL_7 Reset
CPU Access
Note: R/W = Read/Write
Bit
Position
[7:0]
EMAC_HTBL_x
EMAC Hash Table Register
The EMAC Hash Table Register represents the 8x8 hash table matrix. This table is used as
an option to select between different multicast addresses. If a multicast address is
received, the first 6 bits of the CRC are decoded and added to a table that points to a single
bit within the hash table matrix. If the selected bit = 1, the multicast packet is accepted. If
the bit = 0, the multicast packet is rejected. See
Value
00h–
FFh
R/W
Description
This field is the hash table. The 64 bit hash table is
{EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5,
EMAC_HTBL_4, EMAC_HTBL_3, EMAC_HTBL_2,
EMAC_HTBL_1, EMAC_HTBL_0}.
7
0
0
0
0
0
0
0
0
R/W
6
0
0
0
0
0
0
0
0
R/W
5
0
0
0
0
0
0
0
0
R/W
4
0
0
0
0
0
0
0
0
R/W
3
0
0
0
0
0
0
0
0
Table
R/W
2
0
0
0
0
0
0
0
0
197.
Ethernet Media Access Controller
R/W
1
0
0
0
0
0
0
0
0
Product Specification
R/W
0
0
0
0
0
0
0
0
0
eZ80F91 ASSP
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