EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 342

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 223. EMAC Transmit Read Pointer Register—High Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_TRP_H
EMAC Transmit Read Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC Trans-
mit Read Pointer Register are always zero. See
EMAC Receive Blocks Left Register—Low and High Bytes
This register reports the number of buffers left in the Receive EMAC shared memory. The
hardware uses this information along with the block-level set in the EMAC_BUFSZ regis-
ter to determine when to transmit a pause control frame. Software uses this information to
determine when it must request that a pause control frame be transmitted (by setting bit 6
of the EMAC_CFG4 register). For the BlksLeft logic to operate properly, the Receive
buffer must contain at least one more packet buffer than the number of packet buffers
required for the largest packet. That is, one packet cannot fill the entire Receive buffer.
Otherwise, the BlksLeft will be in error. See
Value
00h–1Fh These bits represent the High byte of the 2 byte EMAC
RO
7
0
Description
TxDMA
EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.
RO
6
0
Transmit Read Pointer
RO
5
0
RO
4
0
RO
3
0
Table 224
value, {EMAC_TRP_H,
Table
RO
2
0
223.
and
(EMAC_TRP_H = 0054h)
Table 225
Ethernet Media Access Controller
RO
1
0
Product Specification
RO
0
0
on page 335.
eZ80F91 ASSP
334