EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 58

IC ACCLAIM MCU 256KB 144LQFP

EZ80F91AZA50EG

Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet

Specifications of EZ80F91AZA50EG

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-4563

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91AZA50EG
Manufacturer:
Zilog
Quantity:
10 000
Table 6. GPIO Mode Selection
PS027001-0707
GPIO
Mode
1
2
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 5
pin for the various modes.
GPIO Mode 1—Output
The port pin is configured as a standard digital output pin. The value written to the Port x
Data register (Px_DR) is driven on the pin.
GPIO Mode 2—Input
The port pin is configured as a standard digital input pin. The output is high impedance.
The value stored in the Port x Data register produces no effect. As in all modes, a read
from the Port x Data register returns the pin’s value. GPIO mode 2 is the default operating
mode following a RESET.
Px_ALT1
Bits7:0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
and
Px_DDR
Figure 6
Bits7:0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
on page 53 display the simplified block diagrams of the GPIO port
Bits7:0 Port Mode
Px_DR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Output
Input from pin
Input from pin
Open-drain output
Open-drain I/O
Open-source I/O
Open-source output
Reserved
Interrupt—dual edge-triggered
Alternate function controls port I/O.
Alternate function controls port I/O.
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge-triggered
Interrupt—rising edge-triggered
General Purpose Input/Output
Product Specification
0
1
High impedance
High impedance
0
High impedance
High impedance
1
High impedance
High impedance
Output
High impedance
High impedance
High impedance
High impedance
eZ80F91 ASSP
50

Related parts for EZ80F91AZA50EG