EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 65

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Interrupt Controller
Table 12. Interrupt Vector Sources by Priority
PS027001-0707
Priority
10
0
1
2
3
4
5
6
7
8
9
Maskable Interrupts
Vector
04Ch
05Ch
040h
044h
048h
050h
054h
058h
060h
064h
068h
The interrupt controller on the eZ80F91 device routes the interrupt request signals from
the internal peripherals, external devices (via the internal port I/O), and the nonmaskable
interrupt (NMI) pin to the CPU.
On the eZ80F91 device, all maskable interrupts use the CPU’s vectored interrupt function.
The size of I register is modified to 16 bits in the eZ80F91 device differing from the previ-
ous versions of eZ80
ment. Additionally, the size of the IVECT register is increased from 8 bits to 9 bits to
provide an interrupt vector table that is expanded and more easily integrated with other
interrupts.
The vectors are 4 bytes (32 bits) apart, even though only 3 bytes (24 bits) are required.
A fourth byte is implemented for both programmability and expansion purposes.
Starting the interrupt vectors at
troller vectors with the RST vectors.
for each of the maskable interrupt sources. The maskable interrupt sources are listed in
order of their priority, with vector
the full 24-bit interrupt vector is located at starting address {I[15:1], IVECT[8:0]}, where
I[15:0] is the CPU’s Interrupt Page Address register.
EMAC SYS
EMAC Rx
EMAC Tx
Unused*
Unused*
Source
Timer 0
Timer 1
Timer 2
Timer 3
Flash
PLL
®
CPU, to allow for a 16 MB range of interrupt vector table place-
40h
Priority
40h
allows for easy implementation of the interrupt con-
24
25
26
27
28
29
30
31
32
33
34
Table 12
being the highest-priority interrupt. In ADL mode,
Vector
lists the interrupt vector sources by priority
0ACh
0BCh
0A0h
0A4h
0A8h
0B0h
0B4h
0B8h
0C0h
0C4h
0C8h
Port B 0
Port B 1
Port B 2
Port B 3
Port B 4
Port B 5
Port B 6
Port B 7
Port C 0
Port C 1
Port C 2
Source
Product Specification
eZ80F91 ASSP
Interrupt Controller
57