EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 66

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

Table 12. Interrupt Vector Sources by Priority (Continued)
PS027001-0707
Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable
Priority
11
12
13
14
15
16
17
18
19
20
21
22
23
Note:
interrupt (NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.
Vector
06Ch
07Ch
08Ch
09Ch
070h
074h
078h
080h
084h
088h
090h
094h
098h
The user’s program must store the interrupt service routine starting address in the
four-byte interrupt vector locations. For example in ADL mode, the three-byte address for
the SPI interrupt service routine is stored at {I[15:1], 07Ch}, {I[15:1], 07Dh}, and {I[15:1],
07Eh}. In Z80
{MBASE[7:0], I[7:1], 07Ch} and {MBASE, I[7:1], 07Dh}. The least-significant byte is
stored at the lower address.
When one or more interrupt requests (IRQs) become active, an interrupt request is
generated by the interrupt controller and sent to the CPU. The corresponding 9-bit
interrupt vector for the highest-priority interrupt is placed on the 9-bit interrupt vector bus,
IVECT[8:0]. The interrupt vector bus is internal to the eZ80F91 device and is therefore
externally not visible. The response time of the CPU to an interrupt request is a function of
the current instruction being executed as well as the number of wait states being asserted.
The interrupt vector, {I[15:1], IVECT[8:0]} is visible on the address bus (ADDR[23:0]),
when the interrupt service routine begins. The response of the CPU to a vectored interrupt
on the eZ80F91 device is explained in
to be active until the Interrupt Service Routine (ISR) starts.
The lower bit of the I register is replaced with the MSB of the IVECT from the interrupt
controller. As a result, the interrupt vector table is required to be placed onto a 512-byte
Port A 0
Port A 1
Port A 2
Port A 3
Port A 4
Port A 5
Port A 6
Port A 7
UART 0
UART 1
Source
®
RTC
SPI
I
2
mode, the two-byte address for the SPI interrupt service routine is stored at
C
Priority
35
36
37
38
39
40
41
42
43
44
45
46
47
Table 13
Vector
0CCh
0DCh
0ECh
0D0h
0D4h
0D8h
0FCh
0E0h
0E4h
0E8h
0F0h
0F4h
0F8h
on page 59. Interrupt sources are required
Port C 3
Port C 4
Port C 5
Port C 6
Port C 7
Port D 0
Port D 1
Port D 2
Port D 3
Port D 4
Port D 5
Port D 6
Port D 7
Source
Product Specification
eZ80F91 ASSP
Interrupt Controller
58