EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 76

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Input/Output Chip Select Operation
Wait States
I/O chip selects will be active only when the CPU is performing I/O instructions. Because
the I/O space is separate from the memory space in the eZ80F91 device, a conflict
between I/O and memory addresses never occurs.
The eZ80F91 supports a 16-bit I/O address. The I/O chip select logic decodes the High
byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices are always accessed from memory mode (ADL
or Z80). The MBASE offset value used for setting the Z80 MEMORY mode page is also
always ignored.
Four I/O chip selects are available with the eZ80F91 device. To generate a particular I/O
chip select, the following conditions must be satisfied:
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If all of the foregoing conditions are met to generate an I/O chip select, then the following
results occur:
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For each of the chip selects, programmable Wait states are asserted to provide external
devices with additional clock cycles to complete their Read or Write operations. The
number of wait states for a particular chip select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The Wait states are independently programmed to provide 0
to 7 Wait states for each chip select. The Wait states idle the CPU for the specified number
of system clock cycles.
The chip select is enabled by setting CSx_EN to 1.
The chip select is configured for I/O by setting CSX_IO to 1.
An I/O chip select address match occurs—ADDR[15:8] = CSx_LBR[7:0].
No higher-priority (lower-number) chip select meets the above conditions.
The I/O address is not within the on-chip peripheral address range
On-chip peripheral registers assume priority for all addresses where:
0000h ≤ ADDR[15:0] ≤ 00FFh
An I/O instruction must be executing.
The appropriate chip select—CS0, CS1, CS2, or CS3 is asserted (driven Low).
IORQ is asserted (driven Low).
Depending on the instruction, either RD or WR is asserted (driven Low).
Chip Selects and Wait States
Product Specification
0000h–00FFh
eZ80F91 ASSP
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