C8051F988-GM Silicon Laboratories Inc, C8051F988-GM Datasheet - Page 213
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C8051F988-GM
Manufacturer Part Number
C8051F988-GM
Description
IC MCU 8BIT 4KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F988-GM
Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1959-5
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21. Port Input/Output
Digital and analog resources are available through 16 or 17 I/O pins. Port pins are organized as three byte-
wide ports. Port pins P0.0–P1.7 can be defined as digital or analog I/O. Digital I/O pins can be assigned to
one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by
the internal analog resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal
(C2D). See Section “27. C2 Interface” on page 317 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Port I/Os can tolerate voltages up to the supply rail when used as digital inputs or open-drain outputs.
For Port I/Os configured as push-pull outputs, current is sourced from the V
analog functions can operate up to the V
I/O operating modes and the electrical specifications chapter for detailed electrical specifications.
Highest
Priority
Lowest
Priority
SYSCLK
SMBus
Output
T0, T1
UART
P0
P1
P2
SPI0
CP0
PCA
(P0.0-P0.7)
(P1.0-P1.7)
(P2.7)
Figure 21.1. Port I/O Functional Block Diagram
2
4
2
4
4
2
8
8
1
DD
supply voltage. See Section 21.1 for more information on Port
Rev. 1.0
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Registers
Priority
Digital
(ADC0, CP0, and CP1 inputs,
C8051F99x-C8051F98x
To Analog Peripherals
VREF, IREF0, AGND)
8
8
1
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cell
I/O
I/O
I/O
P0
P1
P2
DD
PnMDIN Registers
External Interrupts
EX0 and EX1
supply. Port I/Os used for
PnMDOUT,
*P1.5 is not available on
20-pin devices.
P0.0
P0.7
P1.0
P1.7*
P2.7
213
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