MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 129
MC68HC908JB8JPE
Manufacturer Part Number
MC68HC908JB8JPE
Description
IC MCU FLASH 8BIT 8K 20-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB8JDWE.pdf
(286 pages)
Specifications of MC68HC908JB8JPE
Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
HC08
No. Of I/o's
13
Ram Memory Size
256Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
USB
Rohs Compliant
Yes
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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9.5.2 Reset Signaling
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
The width of the SE0 in the EOP is about two bit times. The EOP width
is measured with the same capacitive load used for maximum rise and
fall times and is measured at the same level as the differential signal
crossover points of the data lines.
The USB module will detect a reset signaled on the bus by the presence
of an extended SE0 at the USB data pins of a device. The MCU seeing
a single-ended 0 on its USB data inputs for more than 8µs treats that
signal as a reset.
A USB sourced reset will hold the MCU in reset for the duration of the
reset on the USB bus. The USB bit in the reset status register (RSR) will
be set after the internal reset is removed. Refer to
Register
detailed in
t
V
V
V
V
Period
OH
SE
SE
OL
DIFFERENTIAL
DATA LINES
(min.)
(max)
(min.)
(min.)
V
SS
Universal Serial Bus Module (USB)
for more detail. The MCU’s reset recovery sequence is
Section 8. System Integration Module
Figure 9-7. EOP Transaction Voltage Levels
Figure 9-8. EOP Width Timing
LAST BIT OF
PACKET
Universal Serial Bus Module (USB)
CROSSOVER
WIDTH
LEVEL
EOP
STROBE
DATA
EOP
8.8.2 Reset Status
(SIM).
Functional Description
BUS DRIVEN TO
IDLE STATE
Technical Data
BUS FLOATS
BUS IDLE
129
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