MC9S08AC16CFJE Freescale Semiconductor, MC9S08AC16CFJE Datasheet - Page 71

IC MCU 8BIT 16K FLASH 32-LQFP

MC9S08AC16CFJE

Manufacturer Part Number
MC9S08AC16CFJE
Description
IC MCU 8BIT 16K FLASH 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of MC9S08AC16CFJE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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5.9.1
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
Freescale Semiconductor
IRQMOD
IRQEDG
IRQPDD
IRQACK
Reset
IRQPE
IRQIE
Field
IRQF
6
5
4
3
2
1
0
W
R
Interrupt Pin Request Status and Control Register (IRQSC)
Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, it has a pull-down. When the IRQ pin is enabled as the IRQ input and is configured to
detect falling edges, it has a pull-up.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
0
0
7
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
= Unimplemented or Reserved
IRQPDD
0
6
Section 5.5.2.2, “Edge and Level
Table 5-3. IRQSC Register Field Descriptions
IRQEDG
MC9S08AC16 Series Data Sheet, Rev. 8
0
5
IRQPE
0
4
Description
Sensitivity” for more details.
IRQF
Chapter 5 Resets, Interrupts, and System Configuration
3
0
IRQACK
0
0
2
IRQIE
0
1
IRQMOD
0
0
71

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