C8051F540-IQ Silicon Laboratories Inc, C8051F540-IQ Datasheet - Page 127
C8051F540-IQ
Manufacturer Part Number
C8051F540-IQ
Description
IC 8051 MCU 16K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F54xr
Specifications of C8051F540-IQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
32-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1671
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F540-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F540-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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C8051F54x
15.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
15.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Sus-
pend mode. The exception to this is the Port Match feature.
Suspend mode can be terminated by three types of events, a port match (described in Section “18.5. Port
Match” on page 157), a Comparator low output (if enabled), or a device reset event. When Suspend mode
is terminated, the device will continue execution on the instruction following the one that set the SUSPEND
bit. If the wake event was configured to generate an interrupt, the interrupt will be serviced upon waking
the device. If Suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal
reset sequence and begins program execution at address 0x0000.
Note: When entering Suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 7.1).
Rev. 1.1
127
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