C8051F540-IQ Silicon Laboratories Inc, C8051F540-IQ Datasheet - Page 151
C8051F540-IQ
Manufacturer Part Number
C8051F540-IQ
Description
IC 8051 MCU 16K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F54xr
Specifications of C8051F540-IQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
32-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1671
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F540-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F540-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); and similarly when the UART or LIN are selected, the Crossbar assigns both pins associ-
ated with the peripheral (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART
TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contig-
uously after the prioritized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
As an example configuration, if SPI0 in 4-wire mode, and PCA0 Modules 0, 1, and 2 are enabled on the
crossbar with P0.1, P0.2, and P0.5 skipped, the registers should be set as follows: XBR0 = 0x04 (SPI0
enabled), XBR1 = 0x0C (PCA0 modules 0, 1, and 2 enabled), XBR2 = 0x40 (Crossbar enabled), and
P0SKIP = 0x26 (P0.1, P0.2, and P0.5 skipped). The resulting crossbar would look as shown in
Figure 18.4.
Port
Special
Function
Signals
PIN I/O
UART_TX
UART_RX
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX
0 1 2 3
Figure 18.3. Peripheral Availability on Port I/O Pins
P0
4 5 6
7 0 1 2
Rev. 1.1
3 4 5 6
P1
7 0 1 2
available on the 32-pin
P2.2-P2.7, P3.0 only
3 4 5 6
P2
packages
C8051F54x
7 0
P3
151
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