MC908QB4CPE Freescale Semiconductor, MC908QB4CPE Datasheet - Page 169
MC908QB4CPE
Manufacturer Part Number
MC908QB4CPE
Description
IC MCU 8BIT 4K FLASH 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QB8CDWE.pdf
(236 pages)
Specifications of MC908QB4CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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15.7 I/O Signals
The SPI module can share its pins with the general-purpose I/O pins. See
that are shared.
The SPI module has four I/O pins:
15.7.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is 0 and its SS pin is low. To support a multiple-slave system,
a high on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
15.7.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
15.7.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
15.7.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See
be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain
low between transmissions for the CPHA = 1 format. See
Freescale Semiconductor
•
•
•
•
15.3.3 Transmission
MISO — Master input/slave output
MOSI — Master output/slave input
SPSCK — Serial clock
SS — Slave select
Formats.) Because it is used to indicate the start of a transmission, SS must
MC68HC908QB8 Data Sheet, Rev. 3
Figure
15-12.
Figure 15-1
for the port pins
I/O Signals
169
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