C8051F567-IQ Silicon Laboratories Inc, C8051F567-IQ Datasheet - Page 230
C8051F567-IQ
Manufacturer Part Number
C8051F567-IQ
Description
IC 8051 MCU 16K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Specifications of C8051F567-IQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
32-QFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1708
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F567-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
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Company:
Part Number:
C8051F567-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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C8051F55x/56x/57x
22.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. The interrupt will
occur after the ACK cycle.
If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected.
If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received
slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface
enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the
master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the
next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared
(Note: an error condition may be generated if SMB0DAT is written following a received NACK while in
Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the
interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter inter-
rupt. Figure 22.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though any
number of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the
ACK cycle in this mode.
22.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the tables, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown
response options are only the typical responses; application-specific procedures are allowed as long as
they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not con-
form to the SMBus specification.
230
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 22.8. Typical Slave Read Sequence
R
A
Data Byte
Rev. 1.1
Interrupts
A
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
P
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