C8051F320-GQ Silicon Laboratories Inc, C8051F320-GQ Datasheet
C8051F320-GQ
Specifications of C8051F320-GQ
Available stocks
Related parts for C8051F320-GQ
C8051F320-GQ Summary of contents
Page 1
... Supports all USB and UART modes External oscillator: Crystal, RC Clock pin modes) Can switch between clock sources on-the-fly; - useful in power saving strategies RoHS Compliant Packages - 32-pin LQFP (C8051F320) - 28-pin QFN (C8051F321) Temperature Range: –40 to +85 °C ANALOG DIGITAL I/O PERIPHERALS UART SPI + ...
Page 2
... C8051F320/1 2 Rev. 1.4 ...
Page 3
... CIP-51 Microcontroller .......................................................................................... 71 9.1. Instruction Set ................................................................................................... 72 9.1.1. Instruction and CPU Timing ..................................................................... 72 9.1.2. MOVX Instruction and Program Memory ................................................. 73 9.2. Memory Organization........................................................................................ 77 9.2.1. Program Memory...................................................................................... 77 9.2.2. Data Memory............................................................................................ 78 9.2.3. General Purpose Registers ...................................................................... 78 9.2.4. Bit Addressable Locations........................................................................ 78 9.2.5. Stack ....................................................................................................... 78 9.2.6. Special Function Registers....................................................................... 79 C8051F320/1 Rev. 1.4 3 ...
Page 4
... User XRAM ................................................................................... 114 12.2.Accessing USB FIFO Space .......................................................................... 114 13. Oscillators ............................................................................................................. 116 13.1.Programmable Internal Oscillator ................................................................... 116 13.1.1.Programming the Internal Oscillator on C8051F320/1 Devices ............. 117 13.1.2.Internal Oscillator Suspend Mode .......................................................... 118 13.2.External Oscillator Drive Circuit...................................................................... 119 13.2.1.Clocking Timers Directly Through the External Oscillator...................... 119 13.2.2.External Crystal Example....................................................................... 119 13 ...
Page 5
... Low Extension.............................................................................. 171 16.3.3.SCL Low Timeout................................................................................... 171 16.3.4.SCL High (SMBus Free) Timeout .......................................................... 172 16.4.Using the SMBus............................................................................................ 172 16.4.1.SMBus Configuration Register............................................................... 173 16.4.2.SMB0CN Control Register ..................................................................... 176 16.4.3.Data Register ......................................................................................... 179 16.5.SMBus Transfer Modes.................................................................................. 180 16.5.1.Master Transmitter Mode ....................................................................... 180 16.5.2.Master Receiver Mode ........................................................................... 181 C8051F320/1 Rev. 1.4 5 ...
Page 6
... C8051F320/1 16.5.3.Slave Receiver Mode ............................................................................. 182 16.5.4.Slave Transmitter Mode ......................................................................... 183 16.6.SMBus Status Decoding................................................................................. 184 17. UART0.................................................................................................................... 187 17.1.Enhanced Baud Rate Generation................................................................... 188 17.2.Operational Modes ......................................................................................... 188 17.2.1.8-Bit UART ............................................................................................. 189 17.2.2.9-Bit UART ............................................................................................. 190 17.3.Multiprocessor Communications .................................................................... 190 18. Enhanced Serial Peripheral Interface (SPI0)...................................................... 195 18.1.Signal Descriptions......................................................................................... 196 18 ...
Page 7
... Timer Usage ......................................................................... 238 20.4.Register Descriptions for PCA........................................................................ 239 21. C2 Interface ........................................................................................................... 245 21.1.C2 Interface Registers.................................................................................... 245 21.2.C2 Pin Sharing ............................................................................................... 247 C8051F320/1 Rev. 1.4 7 ...
Page 8
... Table 3.1. Global Electrical Characteristics ............................................................. 28 Table 3.2. Index to Electrical Characteristics Tables .............................................. 29 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F320/1 ...................................................... 30 Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 32 Figure 4.2. QFN-28 Pinout Diagram (Top View) ...................................................... 36 5. 10-Bit ADC (ADC0) Figure 5 ...
Page 9
... Figure 15.2. USB0 Register Access Scheme......................................................... 142 Table 15.2. USB0 Controller Registers .................................................................. 144 Figure 15.3. USB FIFO Allocation .......................................................................... 147 Table 15.3. FIFO Configurations ............................................................................ 148 Table 15.4. USB Transceiver Electrical Characteristics ........................................ 168 16. SMBus Figure 16.1. SMBus Block Diagram ....................................................................... 169 C8051F320/1 Rev. 1.4 9 ...
Page 10
... C8051F320/1 Figure 16.2. Typical SMBus Configuration ............................................................. 170 Figure 16.3. SMBus Transaction ............................................................................ 171 Table 16.1. SMBus Clock Source Selection........................................................... 173 Figure 16.4. Typical SMBus SCL Generation......................................................... 174 Table 16.2. Minimum SDA Setup and Hold Times ................................................. 174 Table 16.3. Sources for Hardware Changes to SMB0CN ...................................... 178 Figure 16 ...
Page 11
... Figure 20.8. PCA 8-Bit PWM Mode Diagram ......................................................... 235 Figure 20.9. PCA 16-Bit PWM Mode...................................................................... 236 Figure 20.10. PCA Module 4 with Watchdog Timer Enabled ................................. 237 Table 20.3. Watchdog Timer Timeout Intervals 21. C2 Interface Figure 21.1. Typical C2 Pin Sharing....................................................................... 247 C8051F320/1 1 ................................................................... 239 Rev. 1.4 11 ...
Page 12
... C8051F320/1 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . 46 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 47 SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5 ...
Page 13
... USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte . . 167 USB Register Definition 15.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 167 USB Register Definition 15.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 167 SFR Definition 16.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 175 SFR Definition 16.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 C8051F320/1 Rev. 1.4 13 ...
Page 14
... C8051F320/1 SFR Definition 16.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SFR Definition 17.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SFR Definition 17.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 193 SFR Definition 18.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 203 SFR Definition 18.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 SFR Definition 18.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 SFR Definition 18 ...
Page 15
... Each device is specified for 2.7-to-3.6 V operation over the industrial temperature range (–40 to +85 °C). (Note that 3.0-to-3 required for USB communication.) The Port I/O and /RST pins are tolerant of input signals C8051F320/1 are available in a 32-pin LQFP or a 28-pin QFN package. C8051F320/1 Rev ...
Page 16
... C8051F320/1 Table 1.1. Product Selection Guide C8051F320- 2304 C8051F321- 2304 5.0V Voltage Enable REGIN IN Regulator OUT Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out XTAL1 XTAL2 External Oscillator Circuit 12MHz Internal x4 2 Oscillator 2 USB Clock Clock 1,2,3,4 ...
Page 17
... Reset SRAM SMBus 1 1K byte SPI XRAM C Port 2 o Latch r SFR Bus System e Clock Port 3 Latch VREF VREF USB VDD 10-bit 200ksps ADC SRAM Rev. 1.4 C8051F320/1 P0.0 P P0.1 0 P0.2/XTAL1 P0.3/XTAL2 P0.4 D P0.5 r P0.6/CNVSTR v P0.7/VREF P1.2 P1 P1.5 ...
Page 18
... Number of Instructions 26 1.1.3. Additional Features The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
Page 19
... VDD Supply Monitor Enable + - Power On Reset Comparator C0RSEF Missing Clock Detector (one- PCA shot) Software Reset (SWRSF) WDT EN Errant FLASH EN Operation CIP-51 Microcontroller System Reset Core Extended Interrupt Handler Rev. 1.4 C8051F320/1 '0' /RST (wired-OR) Reset Funnel USB VBUS Controller Transition 19 ...
Page 20
... C8051F320/1 PROGRAM/DATA MEMORY (Flash) RESERVED 0x3E00 0x3DFF 16 K Flash (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 1.4. On-Board Memory Map 1.3. Universal Serial Bus Controller The Universal Serial Bus Controller (USB0 USB 2.0 compliant Full or Low Speed function with inte- grated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT) ...
Page 21
... It also has a target application board with the C8051F320 MCU installed, the necessary cables for connection to a PC, and a wall-mount power supply. The development kit contents may also be used to program and debug the device on the production PCB using the appropriate connections for the program- ming pins ...
Page 22
... I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config- ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “ ...
Page 23
... Figure 1.7. Digital Crossbar Diagram 1.7. Serial Ports The C8051F320/1 Family includes an SMBus/I configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.8. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur- pose counter/timers ...
Page 24
... Analog to Digital Converter The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multi- plexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as ADC inputs ...
Page 25
... Figure 1.10. 10-Bit ADC Block Diagram 1.10. Comparators C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two compar- ator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output ...
Page 26
... CP0RIF CP0FIF CP0HYP1 CMX0N1 CP0HYP0 CMX0N0 CP0HYN1 CP0HYN0 CMX0P1 CMX0P0 P1.0 P1.4 P2.0 P2.4 P1.1 P1.5 P2.1 P2.5 Note: P2.4 and P2.5 available only on C8051F320 Figure 1.11. Comparator0 Block Diagram 26 VDD CP0 + + SET SET CLR CLR (SYNCHRONIZER) GND CP0 - Reset Decision ...
Page 27
... Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F320/1 Conditions Min Typ – ...
Page 28
... C8051F320/1 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise noted. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage 3 SYSCLK (System Clock) T (SYSCLK High Time) SYSH T (SYSCLK Low Time) SYSL Specificed Operating Tem- ...
Page 29
... MHz — < 1 MHz °C — > 1 MHz °C — < 1 MHz °C — > 1 MHz °C — Oscillator not running, — V Monitor disabled DD Rev. 1.4 C8051F320/1 Typ Max Units 0.47 — %/V 0.50 — %/V 0.25 — mA/MHz 0.17 — mA/MHz 0.29 — ...
Page 30
... C8051F320/1 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 ‘F321 Power In VDD 6 6 GND 3 3 /RST C2CK P3. C2D REGIN Power Regulator Input. This pin is the input to the on-chip volt VBUS P0 P0 P0. XTAL1 P0. XTAL2 P0.4 ...
Page 31
... Table 4.1. Pin Definitions for the C8051F320/1 (Continued) Pin Numbers Name Type ‘F320 ‘F321 D I I I I I I I I I I I I I ...
Page 32
... C8051F320/1 P0 GND VDD 6 7 REGIN 8 VBUS Figure 4.1. LQFP-32 Pinout Diagram (Top View) 32 C8051F320 Top View Rev. 1.4 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 ...
Page 33
... Figure 4.2. LQFP-32 Package Drawing Table 4.2. LQFP-32 Package Dimensions Dimension Min A — A1 0.05 A2 1.35 b 0.30 c 0.09 D 9.00 BSC. D1 7.00 BSC. e 0.80 BSC. E 9.00 BSC. E1 7.00 BSC. L 0.45 Rev. 1.4 C8051F320/1 Nom Max — 1.60 — 0.15 1.40 1.45 0.37 0.45 — 0.20 0.60 0.75 33 ...
Page 34
... C8051F320/1 Table 4.2. LQFP-32 Package Dimensions (Continued) Dimension aaa bbb ccc ddd Q Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD- 020 specification for Small Body Components ...
Page 35
... The stencil thickness should be 0.125mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all pads. Card Assembly 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051F320/1 Dimension Min X1 0. ...
Page 36
... C8051F320/1 P0.1 1 P0.0 2 GND VDD 6 REGIN 7 Figure 4.4. QFN-28 Pinout Diagram (Top View) 36 C8051F321 Top View GND Rev. 1.4 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 ...
Page 37
... This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2 and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051F320/1 Max Dimension Min 1. ...
Page 38
... C8051F320/1 Figure 4.6. QFN-28 Recommended PCB Land Pattern Table 4.5. QFN-28 PCB Land Pattern Dimesions Dimension Min C1 4.80 C2 4.80 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. ...
Page 39
... ADC (ADC0) The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...
Page 40
... C8051F320/1 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (V following may be selected as the negative input: P1.0-P3.0, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode ...
Page 41
... Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. = (Gain x Temp ) + Offset Offset) / Gain C TEMP Gain (V / deg C) Offset ( Celsius) Temperature Rev. 1.4 C8051F320 the positive TEMP 41 ...
Page 42
... C8051F320/1 5.0 0 4.0 0 3.0 0 2.0 0 1.0 0 0.0 0 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2. 40.0 0.0 20 Temperature (degrees C) Rev. 1.4 5.0 0 4.0 0 3.0 0 2.0 0 1.0 0 0.0 60.0 80 -1.00 -2.00 -3.00 -4.00 -5.00 ...
Page 43
... CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “14. Port Input/Output” on page 126 for details on Port I/O configuration. C8051F320/1 Rev. 1.4 43 ...
Page 44
... C8051F320/1 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track- ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initi- ate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low ...
Page 45
... MUX Select Figure 5.5. ADC0 Equivalent Input Circuits reduces See Table 5.1 for ADC0 minimum TOTAL MUX n 2 ------ - TOTAL SAMPLE SA Single-Ended Mode MUX Select Px 5pF SAMPLE Input MUX C = 5pF SAMPLE Rev. 1.4 C8051F320 MUX C = 5pF SAMPLE * C SAMPLE 45 ...
Page 46
... Only applies to C8051F320; selection RESERVED on C8051F321 devices. 46 AMX0P: AMUX0 Positive Channel Select R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P1 ...
Page 47
... GND (ADC in Single-Ended Mode) *Note: Only applies to C8051F320; selection RESERVED on C8051F321 devices. AMX0N: AMUX0 Negative Channel Select R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ADC0 Negative Input P1.0 P1 ...
Page 48
... C8051F320/1 SFR Definition 5.3. R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5 ...
Page 49
... ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. ADC0CN: ADC0 Control R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value Bit0 SFR Address: 0xE8 (bit addressable) 49 ...
Page 50
... C8051F320/1 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user- programmed limits, and notifies the system when a desired condition is detected. This is especially effec- tive in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
Page 51
... R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value 00000000 Bit0 SFR Address: 0xC6 R/W Reset Value 00000000 Bit0 SFR Address: 0xC5 51 ...
Page 52
... C8051F320/1 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF * (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value ...
Page 53
... ADC0H:ADC0L Input Voltage (Px.x - Px.y) VREF x (511/512) 0x7FC0 0x1040 VREF x (64/512) 0x1000 0x0FC0 AD0WINT=1 0x0000 VREF x (-1/512) 0xFFC0 0xFF80 0x8000 -VREF Rev. 1.4 C8051F320/1 AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT=1 AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT=1 53 ...
Page 54
... C8051F320/1 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance (10 kHz sine-wave Single-ended input below Full Scale, 200 ksps) ...
Page 55
... Voltage Reference The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected volt- age reference, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to ‘ ...
Page 56
... C8051F320/1 SFR Definition 6.1. R/W R/W R Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. ...
Page 57
... Comparators C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the follow- ing exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be used as a reset source. ...
Page 58
... CP1OUT CP1RIF CP1FIF CP1HYP1 CMX1N1 CP1HYP0 CMX1N0 CP1HYN1 CP1HYN0 CMX1P1 CMX1P0 P1.2 P1.6 P2.2 P2.6 P1.3 P1.7 P2.3 P2.7 Note: P2.6 and P2.7 available only on C8051F320 Figure 7.2. Comparator1 Functional Block Diagram 58 VDD CP1 + + SET SET CLR CLR (SYNCHRONIZER) GND CP1 - ...
Page 59
... CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to ‘1’, and is disabled by clearing this bit to ‘0’. OUT Negative Hysteresis Voltage (Programmed by CP0HYN Bits) Negative Hysteresis Maximum Disabled Negative Hysteresis Maximum Positive Hysteresis Rev. 1.4 C8051F320/1 59 ...
Page 60
... C8051F320/1 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. ...
Page 61
... Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 Positive Input *Note: P2.4 and P2.5 available only on C8051F320 devices; selection reserved on C8051F321 devices. R/W R/W R/W R CMX0P1 CMX0P0 00000000 Bit4 Bit3 Bit2 Bit1 P1 ...
Page 62
... C8051F320/1 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. ...
Page 63
... Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit4 Bit3 Bit2 Rev. 1.4 C8051F320/1 R/W R/W Reset Value Bit1 Bit0 SFR Address: 0x9A 63 ...
Page 64
... Bits1–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P1 CMX1P0 *Note: P2.6 and P2.7 available only on C8051F320 devices; selection reserved on C8051F321 devices. 64 R/W R/W R CMX1P1 CMX1P0 00000000 Bit4 Bit3 Bit2 P1 ...
Page 65
... These bits select the response time for Comparator1. Mode CP1MD1 CP1MD0 R/W R/W R/W R CP1MD1 CP1MD0 00000010 Bit4 Bit3 Bit2 Bit1 CP1 Response Time (TYP) 0 100 ns 1 175 ns 0 320 ns 1 1050 ns Rev. 1.4 C8051F320/1 R/W Reset Value Bit0 SFR Address: 0x9C 65 ...
Page 66
... C8051F320/1 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 DD unless otherwise noted. Parameter Response Time: Mode 0, Vcm* = 1.5 V Response Time: Mode 1, Vcm* = 1.5 V Response Time: Mode 2, Vcm* = 1.5 V Response Time: Mode 3, Vcm ...
Page 67
... Voltage Regulator (REG0) C8051F320/1 devices include a 5-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. ...
Page 68
... Bias Current 3 Dropout Voltage ( Notes: 1. Input range specified for regulation. When an external regulator is used, REGIN should be tied to 2. Output current is total regulator output, including any current required by the C8051F320/1. 3. The minimum input voltage is 2. VDD + V VBUS From VBUS REGIN To 3V VDD Power Net Figure 8 ...
Page 69
... VBUS From VBUS REGIN From 3V VDD Power Net Figure 8.4. REG0 Configuration: USB Self-Powered, Regulator Disabled C8051F320/1 C8051F320/1 VBUS Sense 5V In Voltage Regulator (REG0) 3V Out C8051F320/1 VBUS Sense 5V In Voltage Regulator (REG0) 3V Out Rev. 1.4 Device Power Net Device Power Net 69 ...
Page 70
... This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regu- lator operates in low power (suspend) mode. 0: USB0 Voltage Regulator in normal mode. 1: USB0 Voltage Regulator in low power mode. Bits3–0: Reserved. Read = 0000b. Must Write = 0000b. 70 C8051F320/1 VBUS Sense 5V In Voltage Regulator (REG0) VDD R/W ...
Page 71
... DATA BUS B REGISTER STACK POINTER TMP1 TMP2 SRAM ADDRESS (256 X 8) ALU REGISTER DATA BUS BUFFER D8 SFR BUS D8 SFR_WRITE_DATA D8 INTERFACE SFR_READ_DATA D8 MEMORY MEM_WRITE_DATA A16 INTERFACE MEM_READ_DATA PIPELINE D8 INTERRUPT INTERFACE D8 D8 REGISTER Rev. 1.4 C8051F320/1 SRAM SFR_ADDRESS SFR_CONTROL MEM_ADDRESS MEM_CONTROL SYSTEM_IRQs EMULATION_IRQ 71 ...
Page 72
... C8051F320/1 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
Page 73
... MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses external RAM (XRAM) and the on-chip program memory space implemented as re-programmable Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “ ...
Page 74
... C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ORL direct direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A ...
Page 75
... Compare immediate to indirect and jump if not CJNE @Ri, #data, rel equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Boolean Manipulation Program Branching Rev. 1.4 C8051F320/1 Clock Bytes Cycles ...
Page 76
... C8051F320/1 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. ...
Page 77
... Byte Sectors) 0x0000 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F320/1 implements 16k bytes of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL ...
Page 78
... C8051F320/1 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
Page 79
... TMR2H AMX0P ADC0CF ADC0L OSCICL SPI0DAT P0MDOUT P1MDOUT P2MDOUT CPT0CN CPT1MD CPT0MD TMR3L TMR3H TL1 TH0 TH1 DPH 3(B) 4(C) 5(D) Rev. 1.4 C8051F320/1 VDM0CN EIP1 EIP2 RSTSRC EIE1 EIE2 PCA0CPM 4 P2SKIP USB0XCN ADC0LTH ADC0H FLSCL FLKEY P3MDOUT CPT1MX CPT0MX USB0ADR ...
Page 80
... C8051F320/1 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ...
Page 81
... PCA Capture 2 Low PCA0CPL3 0xED PCA Capture 3Low PCA0CPL4 0xFD PCA Capture 4 Low PCA0CPM0 0xDA PCA Module 0 Mode Register PCA0CPM1 0xDB PCA Module 1 Mode Register C8051F320/1 Description Rev. 1.4 Page 96 118 118 121 133 133 133 134 134 134 135 ...
Page 82
... C8051F320/1 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address PCA0CPM2 0xDC PCA Module 2 Mode Register PCA0CPM3 0xDD PCA Module 3 Mode Register PCA0CPM4 0xDE PCA Module 4 Mode Register PCA0H 0xFA PCA Counter High ...
Page 83
... The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. Description DPL: Data Pointer Low Byte R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 Page 221 225 226 226 226 226 143 144 141 101 131 ...
Page 84
... C8051F320/1 SFR Definition 9.2. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. SFR Definition 9.3. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SP: Stack Pointer. ...
Page 85
... This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. PSW: Program Status Word R/W R/W R/W R/W RS1 RS0 OV F1 Bit4 Bit3 Bit2 Bit1 Address 0 0x00–0x07 1 0x08–0x0F 2 0x10–0x17 3 0x18–0x1F Rev. 1.4 C8051F320/1 R Reset Value PARITY 00000000 Bit0 SFR Address: 0xD0 (bit addressable) 85 ...
Page 86
... C8051F320/1 SFR Definition 9.5. R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9.6. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. ...
Page 87
... ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ- ated vector addresses, priority order and control bits are summarized in Table 9.4 on page 89. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051F320/1 Rev. 1.4 87 ...
Page 88
... C8051F320/1 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “19.1. Timer 0 and Timer 1” on page 209) select level or edge sensitive ...
Page 89
... Y TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) 6 MODF (SPI0CN.5) Y RXOVRN (SPI0CN. (SMB0CN. Special N AD0WINT 9 Y (ADC0CN.3) Rev. 1.4 C8051F320/1 Enable Priority Flag Control Always Always Enabled Highest PX0 Y EX0 (IE.0) (IP.0) Y ET0 (IE.1) PT0 (IP.1) PX1 Y EX1 (IE.2) (IP.2) Y ET1 (IE.3) PT1 (IP.3) ...
Page 90
... C8051F320/1 Table 9.4. Interrupt Summary (Continued) Interrupt Interrupt Source Vector ADC0 Conversion 0x0053 Complete Programmable 0x005B Counter Array Comparator0 0x0063 Comparator1 0x006B Timer 3 Overflow 0x0073 VBUS Level 0x007B 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s) ...
Page 91
... This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. IE: Interrupt Enable R/W R/W R/W R/W ES0 ET1 EX1 ET0 Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value EX0 00000000 Bit0 SFR Address: 0xA8 (bit addressable) 91 ...
Page 92
... C8051F320/1 SFR Definition 9.8. R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1b, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. ...
Page 93
... This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. EIE1: Extended Interrupt Enable 1 R/W R/W R/W EPCA0 EADC0 EWADC0 EUSB0 Bit4 Bit3 Bit2 Rev. 1.4 C8051F320/1 R/W R/W Reset Value ESMB0 00000000 Bit1 Bit0 SFR Address: 0xE6 93 ...
Page 94
... C8051F320/1 SFR Definition 9.10. R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. Bit6: PCP1: Comparator1 (CP1) Interrupt Priority Control. ...
Page 95
... EIE2: Extended Interrupt Enable 2 R/W R/W R/W R Bit4 Bit3 Bit2 Bit1 EIP2: Extended Interrupt Priority 2 R/W R/W R/W R Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value - EVBUS 00000000 Bit0 SFR Address: 0xE7 R/W Reset Value PVBUS 00000000 Bit0 SFR Address: 0xF7 95 ...
Page 96
... C8051F320/1 SFR Definition 9.13. R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 19.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde- pendent of the Crossbar ...
Page 97
... If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU put to in STOP mode for longer than the MCD timeout of 100 µsec. C8051F320/1 Rev. 1.4 97 ...
Page 98
... C8051F320/1 SFR Definition 9.14. R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. ...
Page 99
... Figure 10.1. Reset Sources VDD Supply Monitor Enable + - Power On Reset + - C0RSEF Missing Clock Detector (one- PCA shot) Software Reset (SWRSF) WDT EN Errant FLASH EN Operation CIP-51 Microcontroller System Reset Core Extended Interrupt Handler Rev. 1.4 C8051F320/1 '0' /RST (wired-OR) Reset Funnel USB VBUS Controller Transition 99 ...
Page 100
... C8051F320/1 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above Power-On Reset delay (T RST PORDelay typically less than 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing. ...
Page 101
... VDD below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. Bits5–0: Reserved. Read = Variable. Write = don’t care. VDM0CN: VDD Monitor Control Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 , the power supply RST R Reset Value Variable Bit0 SFR Address: 0xFF 101 ...
Page 102
... C8051F320/1 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete /RST pin specifications ...
Page 103
... The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register REG0CN. See Section “8. Voltage Regulator (REG0)” on page 67 for details on the VBUS detection circuit. The USBRSF bit will read ‘1’ following a USB reset. The state of the /RST pin is unaffected by this reset. C8051F320/1 Rev. 1.4 103 ...
Page 104
... C8051F320/1 SFR Definition 10.2. R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. Bit6: FERROR: Flash Error Indicator. ...
Page 105
... Minimum /RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply Current Conditions Min = 8.5 mA, VDD = 2 3.6 V 0.7 x VDD 2.40 100 100 Rev. 1.4 C8051F320/1 Typ Max Units 0 0.3 x VDD 25 40 µA 2.55 2.70 V ...
Page 106
... C8051F320/1 11. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution ...
Page 107
... Data is written using the MOVX write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. Conditions Min 16384* 20k 10 40 Rev. 1.4 C8051F320/1 Typ Max Units bytes 100k Erase/Write 15 20 ...
Page 108
... Flash Error system reset will be generated. Locked when any other Flash pages are locked Access limit set according to the Flash security lock byte Figure 11.1. Flash Program Memory Map and Security Byte 108 C8051F320/1 Reserved 0x3E00 Lock Byte 0x3DFF 0x3DFE 0x3C00 Flash memory organized in 512-byte pages ...
Page 109
... Locking any Flash page also locks the page containing the Lock Byte. - Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase user code writes to the Lock Byte, the Lock does not take effect until the next device reset. C8051F320/1 C2 Debug User Firmware executing from: ...
Page 110
... C8051F320/1 11.4. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi- fying code can result in alteration of Flash memory contents causing a system failure that is only recover- able by re-Flashing the code in the device ...
Page 111
... CMOS clock. 13. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase operations. The external oscillator can continue to run, and the CPU can switch back to the external oscillator after the Flash operation has completed. C8051F320/1 Rev. 1.4 111 ...
Page 112
... C8051F320/1 SFR Definition 11.1. R/W R/W R Bit7 Bit6 Bit5 Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to be erased ...
Page 113
... MHz, disabling the Flash one-shot will increase system power consumption. 0: Flash one-shot disabled. 1: Flash one-shot enabled. Bits6–0: RESERVED. Read = 000000b. Must Write 000000b. FLSCL: Flash Scale R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value Bit0 SFR Address: 0xB6 113 ...
Page 114
... C8051F320/1 12. External RAM The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF). 0xFFFF Same 2048 bytes as from 0x0000 to 0x07FF, wrapped 0x0800 0x07FF 0x0400 0x03FF 0x0000 Figure 12 ...
Page 115
... Endpoint3 (512 bytes) 0x0440 0x043F Free (64 bytes) 0x0400 EMI0CN: External Memory Interface Control R/W R/W R PGSEL2 PGSEL1 Bit4 Bit3 Bit2 Rev. 1.4 C8051F320/1 USB FIFO Space (USB Clock Domain) R/W R/W Reset Value PGSEL0 00000000 Bit1 Bit0 SFR Address: 0xAA 115 ...
Page 116
... Figure 13.1. Oscillator Diagram 13.1. Programmable Internal Oscillator All C8051F320/1 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register as defined by is the frequency of the internal oscillator following a reset, T is the change in Equation 13 ...
Page 117
... Equation 13.1. Typical Change in Internal Oscillator Period with OSCICL T 0.0025 On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (f tion 13.1.1 details oscillator programming for C8051F320/1 devices. Electrical specifications for the preci- sion internal oscillator are given in Table 13.3 on page 125. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
Page 118
... C8051F320/1 Important Note: If the sum of the reset value of OSCICL and OSCICL is greater than 31 or less than 0, then the device will not be capable of producing the desired frequency. 13.1.2. Internal Oscillator Suspend Mode The internal oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register OSCICN ...
Page 119
... Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. C8051F320/1 Rev. 1.4 119 ...
Page 120
... C8051F320/1 13.2.3. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation ...
Page 121
... MHz 1.6 MHz f 3.2 MHz Rev. 1.4 C8051F320/1 R/W Reset Value XFCN0 00000000 Bit0 ...
Page 122
... C8051F320/1 13.3. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “15.4. USB Clock Configuration” on page 146). A divided version of the Multiplier output can also be used as the system clock. See Section 13.4 for details on system clock and USB clock source selection ...
Page 123
... Clock Multiplier USBCLK = 000b Internal Oscillator* MULSEL = 00b Divide by 1 IFCN = 11b External Oscillator Input Source Selection Register Bit Settings Clock Multiplier USBCLK = 000b External Oscillator MULSEL = 01b Crystal Oscillator Mode XOSCMD = 110b 12 MHz Crystal XFCN = 111b Rev. 1.4 C8051F320/1 123 ...
Page 124
... C8051F320/1 Table 13.2. Typical USB Low Speed Clock Settings Clock Signal USB Clock Internal Oscillator Clock Signal USB Clock External Oscillator SFR Definition 13.5. CLKSEL: Clock Select R/W R/W R/W - USBCLK Bit7 Bit6 Bit5 Bit 7: Unused. Read = 0b; Write = don’t care. ...
Page 125
... Internal Oscillator Supply Current (from VDD) USB Clock Frequency* *Note: Applies only to external oscillator sources. Conditions Min Reset Frequency 11.82 OSCICN Full Speed Mode 47.88 Low Speed Mode 5.91 Rev. 1.4 C8051F320/1 Typ Max Units 12 12.18 MHz 450 µA 48 48.12 MHz 6 6.09 ...
Page 126
... C8051F320/1 14. Port Input/Output Digital and analog resources are available through 25 I/O pins (C8051F320 I/O pins (C8051F321). Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 14 ...
Page 127
... PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram Rev. 1.4 C8051F320/1 VDD VDD (WEAK) PORT PAD GND 127 ...
Page 128
... C8051F320/1 14.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5 Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource ...
Page 129
... Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin *NSS is only pinned out in 4-wire SPI mode P1SKIP[0:7] Rev. 1.4 C8051F320 P2SKIP[0:3] 129 ...
Page 130
... C8051F320/1 14.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT) ...
Page 131
... URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. R/W R/W R/W R/W CP0E SYSCKE SMB0E SPI0E Bit4 Bit3 Bit2 Rev. 1.4 C8051F320/1 R/W Reset Value URT0E 00000000 Bit1 Bit0 SFR Address: 0xE1 131 ...
Page 132
... C8051F320/1 SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull output). 1: Weak Pull-ups disabled. ...
Page 133
... R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value P0.0 11111111 Bit0 SFR Address: 0x80 (bit addressable) R/W Reset Value 11111111 Bit0 SFR Address: 0xF1 R/W Reset Value ...
Page 134
... C8051F320/1 SFR Definition 14.6. P0SKIP: Port0 Skip Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar ...
Page 135
... Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. Note: P2.7–P2.4 only available on C8051F320 devices. Writes to these Ports do not require XBARE = ‘1’. R/W R/W ...
Page 136
... Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis- ter P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. Note: P2.7–P2.4 only available on C8051F320 devices. SFR Definition 14.14. P2SKIP: Port2 Skip Register R/W R/W ...
Page 137
... R/W R Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value P3.0 11111111 Bit0 SFR Address: 0xB0 (bit addressable) R/W Reset Value - 00000001 Bit0 SFR Address: 0xF4 R/W Reset Value - 00000000 Bit0 SFR Address: ...
Page 138
... C8051F320/1 Table 14.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull Output High Voltage –10 µA, Port I/O push-pull –10 mA, Port I/O push-pull OH Output Low Voltage Input High Voltage Input Low Voltage ...
Page 139
... Universal Serial Bus Controller (USB) C8051F320/1 devices include a complete Full/Low Speed USB function for USB peripheral implementa- tions*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mech- anism for crystal-less operation ...
Page 140
... C8051F320/1 15.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 15.1. Endpoint Addressing Scheme Endpoint Associated Pipes Endpoint0 Endpoint0 OUT ...
Page 141
... Dn: D- Signal Status This bit indicates the current logic level of the D– pin. 0: D– signal currently at logic 0. 1: D– signal currently at logic 1. R/W R Bit4 Bit3 Bit2 Bit1 Mode D+ D– Rev. 1.4 C8051F320/1 R Reset Value Dn 00000000 Bit0 SFR Address: 0xD7 141 ...
Page 142
... C8051F320/1 15.3. USB Register Access The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 15.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end- point number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “ ...
Page 143
... USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. R/W R/W R/W R/W USBADDR Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value 00000000 Bit0 SFR Address: 0x96 143 ...
Page 144
... C8051F320/1 SFR Definition 15.3. USB0DAT: USB0 Data R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. ...
Page 145
... Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte R R/W R/W R/W - EPSEL Bit4 Bit3 Bit2 Bit1 Reserved Rev. 1.4 C8051F320/1 Page Number 160 163 164 166 167 161 167 167 R/W Reset Value 00000000 Bit0 USB Address: 0x0E 145 ...
Page 146
... C8051F320/1 15.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “ ...
Page 147
... IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see Figure 15.20). C8051F320/1 Configurable as IN, OUT, or both (Split ...
Page 148
... C8051F320/1 15.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint ...
Page 149
... Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = ‘1’). The Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as R/W R/W R/W R/W Function Address Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value 00000000 Bit0 USB Address: 0x00 149 ...
Page 150
... C8051F320/1 disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section “13. Oscillators” on page 116 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener- ated, (2) Reset signaling is detected, or (3) a device or USB reset occurs ...
Page 151
... Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. R/W R/W R/W R USBRST RESUME SUSMD Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value SUSEN 00010000 Bit0 USB Address: 0x01 151 ...
Page 152
... C8051F320/1 USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 15.10. FRAMEH: USB0 Frame Number High Bit7 Bit6 Bit5 Bits7-3: Unused. Read = 0. Write = don’t care. ...
Page 153
... IN Endpoint 1 interrupt active. Bit0: EP0: Endpoint 0 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active IN3 IN2 IN1 Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R Reset Value EP0 00000000 Bit0 USB Address: 0x02 153 ...
Page 154
... C8051F320/1 USB Register Definition 15.12. OUT1INT: USB0 Out Endpoint Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 3 interrupt inactive. ...
Page 155
... Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active SOF RSTINT RSUINT Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R Reset Value SUSINT 00000000 Bit0 USB Address: 0x06 155 ...
Page 156
... C8051F320/1 USB Register Definition 15.14. IN1IE: USB0 IN Endpoint Interrupt Enable R/W R/W R Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled Endpoint 3 interrupt enabled. Bit2: IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled ...
Page 157
... Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). R/W R/W R/W R/W - SOFE RSTINTE RSUINTE SUSINTE 00000110 Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value Bit0 USB Address: 0x0B 157 ...
Page 158
... C8051F320/1 The E0CNT register (Figure 15.18) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘ ...
Page 159
... Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the STALL is transmitted. C8051F320/1 Rev. 1.4 159 ...
Page 160
... C8051F320/1 USB Register Definition 15.17. E0CSR: USB0 Endpoint0 Control R/W R/W R/W SSUEND SOPRDY SDSTL Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND. ...
Page 161
... INPRDY bit, and generate an interrupt. Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token E0CNT Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R Reset Value 00000000 Bit0 USB Address: 0x16 161 ...
Page 162
... C8051F320/1 A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware gener- ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’. The STSTL bit must be reset to ‘ ...
Page 163
... SOF is received. An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a packet being transmitted. R/W W R/W SDSTL FLUSH UNDRUN FIFONE Bit4 Bit3 Bit2 Rev. 1.4 C8051F320/1 R/W R/W Reset Value INPRDY 00000000 Bit1 Bit0 USB Address: 0x11 163 ...
Page 164
... C8051F320/1 USB Register Definition 15.20. EINCSRH: USB0 IN Endpoint Control High Byte R/W R/W R/W DBIEN ISO DIRSEL Bit7 Bit6 Bit5 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. Bit6: ISO: Isochronous Transfer Enable. ...
Page 165
... FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be gen- erated, and the DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO. C8051F320/1 Rev. 1.4 165 ...
Page 166
... C8051F320/1 USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte W R/W R/W CLRDT STSTL SDSTL Bit7 Bit6 Bit5 Bit7: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’. ...
Page 167
... Bit4 Bit3 Bit2 Bit1 EOCL Bit4 Bit3 Bit2 Bit1 Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R Reset Value - 00000000 Bit0 USB Address: 0x15 R Reset Value 00000000 Bit0 USB Address: 0x16 R Reset Value E0CH 00000000 Bit0 USB Address: 0x17 167 ...
Page 168
... C8051F320/1 Table 15.4. USB Transceiver Electrical Characteristics V = 3.0 to 3.6V, –40 to +85 °C unless otherwise specified. DD Parameters Symbol Transmitter V Output High Voltage OH V Output Low Voltage OL V Output Crossover Point CRS Z Output Impedance DRV R Pull-up Resistance PU T Output Rise Time R T Output Fall Time ...
Page 169
... SCL Generation (Master Mode) SDA Control IRQ Generation Figure 16.1. SMBus Block Diagram Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL N Control Data Path SDA Control Control SMB0DAT FILTER N Rev. 1.4 C8051F320/1 C serial bus. Reads and writes to SCL Port I SDA 169 ...
Page 170
... C8051F320/1 16.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. ...
Page 171
... SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. C8051F320/1 R/W D7 ...
Page 172
... C8051F320/1 16.3.4. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a Master START, the START will be generated following this timeout ...
Page 173
... SMBus bit rate is approximated by Equation 16.2. Equation 16.2. Typical SMBus Bit Rate BitRate SMBCS SMBus Clock Source 0 0 Timer 0 Overflow 1 Timer 1 Overflow 0 Timer 2 High Byte Overflow 1 Timer 2 Low Byte Overflow 1 --------------------------------------------- - = T = LowMin f ClockSourceOverflow f ClockSourceOverflow --------------------------------------------- - = 3 Rev. 1.4 C8051F320/1 173 ...
Page 174
... C8051F320/1 Figure 16.4 shows the typical SCL generation described by Equation 16.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 16 ...
Page 175
... The selected device should be configured according to Equation 16.1. SMBCS1 SMBCS0 SMB0CF: SMBus Clock/Configuration R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow Rev. 1.4 C8051F320/1 R/W Reset Value Bit0 SFR 0xC1 Address: 175 ...
Page 176
... C8051F320/1 16.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see Figure 16.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes, respectively ...
Page 177
... This bit is set by hardware under the conditions listed in Table 16.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. SMB0CN: SMBus Control R R/W STO ACKRQ ARBLOST ACK Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value SI 00000000 Bit0 Bit Addressable 0xC0 SFR Address: 177 ...
Page 178
... C8051F320/1 Table 16.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed by an address byte is STA received. • A STOP is detected while addressed as a STO slave ...
Page 179
... SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. SMB0DAT: SMBus Data R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value 00000000 Bit0 0xC2 SFR Address: 179 ...
Page 180
... C8051F320/1 16.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames ...
Page 181
... ACK cycle in this mode. S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 16.6. Typical Master Receiver Sequence R A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Rev. 1.4 C8051F320 Interrupt 181 ...
Page 182
... C8051F320/1 16.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set ...
Page 183
... Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA R A Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 16.8. Typical Slave Transmitter Sequence Data Byte A Data Byte N Interrupt Interrupt S = START P = STOP N = NACK R = READ SLA = Slave Address Rev. 1.4 C8051F320/1 Interrupt P 183 ...
Page 184
... C8051F320/1 16.6. SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification ...
Page 185
... An illegal STOP or bus error was 0101 detected while a Slave Transmis- sion was in progress. C8051F320/1 Typical Response Options Acknowledge received byte; Read SMB0DAT. Send NACK to indicate last byte, and send STOP. Send NACK to indicate last byte, and send STOP fol- lowed by START ...
Page 186
... C8051F320/1 Table 16.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave address was received ACK requested. 0010 Lost arbitration as master; slave address received; ACK requested. Lost arbitration while attempting a 0010 repeated START. Lost arbitration while attempting STOP. A STOP was detected while ...
Page 187
... Q TX CLR Zero Detector Shift Data Tx Control Send Tx IRQ SCON TI Serial Port Interrupt RI Rx IRQ Rx Control Load SBUF Shift 0x1FF RB8 Input Shift Register (9 bits) Load SBUF SBUF (RX Latch) Read SBUF SFR Bus RX Rev. 1.4 C8051F320/1 Crossbar Port I/O Crossbar 187 ...
Page 188
... C8051F320/1 17.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 17.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
Page 189
... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 17.4. 8-Bit UART Timing Diagram TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR MCU C8051Fxxx Rev. 1.4 C8051F320/1 STOP D6 D7 BIT 189 ...
Page 190
... C8051F320/1 17.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
Page 191
... Master Slave Device Device Figure 17.6. UART Multi-Processor Mode Interconnect Diagram C8051F320/1 Slave Slave Device Device Rev. 1.4 V+ 191 ...
Page 192
... C8051F320/1 SFR Definition 17.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b. Write = don’ ...
Page 193
... SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con- tents of the receive latch. R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.4 C8051F320/1 R/W Reset Value 00000000 Bit0 0x99 SFR Address: 193 ...
Page 194
... C8051F320/1 Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Target Actual Baud Rate Baud Rate Baud Rate Error (bps) (bps) 230400 230769 0.16% 115200 115385 0.16% 57600 57692 0.16% 28800 28846 0.16% 14400 14423 0.16% 9600 9615 ...
Page 195
... SFR Bus Figure 18.1. SPI Block Diagram SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK Pin Control Logic Shift Register MISO Rx Data NSS Read SPI0DAT Rev. 1.4 C8051F320/1 SPI IRQ Port I 195 ...
Page 196
... C8051F320/1 18.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 18.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
Page 197
... SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 18.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. C8051F320/1 Rev. 1.4 197 ...
Page 198
... C8051F320/1 Master Device 1 Figure 18.2. Multiple-Master Mode Connection Diagram Master Device Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 18.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig- nal ...
Page 199
... The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 18.3 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is C8051F320/1 Rev. 1.4 199 ...
Page 200
... C8051F320/1 slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency ...