R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 472
R5F212B7SNFP#U0
Manufacturer Part Number
R5F212B7SNFP#U0
Description
IC R8C/2B MCU FLASH 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Br
Specifications of R5F212B7SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 16.46
16.3.5
Figures 16.46 to 16.49 show Examples of Register Setting When Using I
Nov 26, 2007
Examples of Register Setting
Example of Register Setting in Master Transmit Mode (I
ICCR1 register
ICCR2 register
ICSR register
ICSR register
ICCR2 register
ICCR1 register
ICSR register
Read STOP bit in ICSR register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Read ACKBR bit in ICIER register
Read BBSY bit in ICCR2 register
Read TEND bit in ICSR register
Read TDRE bit in ICSR register
Read TEND bit in ICSR register
No
No
No
No
No
No
Page 450 of 580
ACKBR = 0 ?
Initial setting
BBSY = 0 ?
Yes
TEND = 1 ?
TDRE = 1 ?
TEND = 1 ?
Last byte ?
STOP = 1 ?
TDRE bit ← 0
Transmit
mode ?
TEND bit ← 0
TRS bit ← 1
MST bit ← 1
SCP bit ← 0
BBSY bit ← 1
SCP bit ← 0
BBSY bit ← 0
TRS bit ← 0
MST bit ← 0
STOP bit ← 0
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Master receive
mode
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
• Set the MSTIIC bit in the MSTCR register to 1.
(1) Judge the state of the SCL and SDA lines
(2) Set to master transmit mode
(3) Generate the start condition
(4) Set the transmit data of the 1st byte
(5) Wait for 1 byte to be transmitted
(6) Judge the ACKBR bit from the specified slave device
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait until the ICRDT register is empty
(9) Set the transmit data of the last byte
(10) Wait for end of transmission of the last byte
(11) Set the TEND bit to 0
(12) Set the STOP bit to 0
(13) Generate the stop condition
(14) Wait until the stop condition is generated
(15) Set to slave receive mode
(slave address + R/W)
Set the TDRE bit to 0
16. Clock Synchronous Serial Interface
2
C bus interface.
2
C bus Interface Mode)
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